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tests: update testbench for controller reg map

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Phil
2026-07-14 16:34:35 +03:00
parent 984461afc0
commit e467700368
3 changed files with 150 additions and 19 deletions
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82
rtl/controller/tests/tb_controller_wrapper_axil.sv
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@ -1,8 +1,22 @@
module tb_controller_wrapper_axil #(
parameter int unsigned DAC_DATA_WIDTH = 12,
parameter int unsigned ADDR_W = 16,
parameter int unsigned DATA_W = 32,
parameter int unsigned USER_W = 1
parameter int unsigned ADDR_W = 16,
parameter int unsigned DATA_W = 32,
parameter int unsigned USER_W = 1,
parameter int unsigned DAC_DATA_WIDTH = 12,
parameter int unsigned AXI_ADDR_WIDTH = 16,
parameter int unsigned AXIS_ID_WIDTH = 8,
parameter int unsigned LEN_WIDTH = 20,
parameter int unsigned AXIS_USER_WIDTH = 1,
parameter int unsigned AXIS_DEST_WIDTH = 8,
parameter int unsigned TAG_WIDTH = 8,
parameter int unsigned READ_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH,
parameter int unsigned WRITE_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH,
parameter int unsigned READ_STATUS_WIDTH = TAG_WIDTH + 4,
parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4
)(
input logic ctrl_clk,
input logic rst,
@ -35,6 +49,7 @@ module tb_controller_wrapper_axil #(
logic rst_n;
assign rst_n = ~rst;
// Для минимального теста держим все clock domain-ы на одном clock.
logic dac_clk_in;
logic adc_clk_in;
assign dac_clk_in = ctrl_clk;
@ -84,6 +99,7 @@ module tb_controller_wrapper_axil #(
.m_axil(axil_bus)
);
// Controller ADC/DAC outputs.
logic [31:0] adc_window_size;
logic [31:0] dac_pulse_width;
logic [31:0] dac_pulse_period;
@ -96,11 +112,45 @@ module tb_controller_wrapper_axil #(
logic dac_rst;
logic adc_rst;
// DMA side. Для базового AXI-Lite теста даём спокойные значения.
logic ready_desc_read;
logic ready_desc_write;
logic ready_status_read;
logic ready_status_write;
logic valid_desc_read;
logic valid_desc_write;
logic valid_status_read;
logic valid_status_write;
logic [READ_STATUS_WIDTH-1:0] status_read_cmd_in;
logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd_in;
logic [READ_DESC_WIDTH-1:0] desc_read_cmd_out;
logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd_out;
assign ready_desc_read = 1'b1;
assign ready_desc_write = 1'b1;
assign valid_status_read = 1'b0;
assign valid_status_write = 1'b0;
assign status_read_cmd_in = '0;
assign status_write_cmd_in = '0;
controller_wrapper_axil #(
.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
.ADDR_W(ADDR_W),
.DATA_W(DATA_W),
.USER_W(USER_W)
.USER_W(USER_W),
.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXIS_ID_WIDTH(AXIS_ID_WIDTH),
.LEN_WIDTH(LEN_WIDTH),
.AXIS_USER_WIDTH(AXIS_USER_WIDTH),
.AXIS_DEST_WIDTH(AXIS_DEST_WIDTH),
.TAG_WIDTH(TAG_WIDTH),
.READ_DESC_WIDTH(READ_DESC_WIDTH),
.WRITE_DESC_WIDTH(WRITE_DESC_WIDTH),
.READ_STATUS_WIDTH(READ_STATUS_WIDTH),
.WRITE_STATUS_WIDTH(WRITE_STATUS_WIDTH)
) dut (
.ctrl_clk(ctrl_clk),
.dac_clk_in(dac_clk_in),
@ -122,7 +172,25 @@ module tb_controller_wrapper_axil #(
.dac_start(dac_start),
.adc_start(adc_start),
.dac_rst(dac_rst),
.adc_rst(adc_rst)
.adc_rst(adc_rst),
.ready_desc_read(ready_desc_read),
.ready_desc_write(ready_desc_write),
.ready_status_read(ready_status_read),
.ready_status_write(ready_status_write),
.valid_desc_read(valid_desc_read),
.valid_desc_write(valid_desc_write),
.valid_status_read(valid_status_read),
.valid_status_write(valid_status_write),
.status_read_cmd_in(status_read_cmd_in),
.status_write_cmd_in(status_write_cmd_in),
.desc_read_cmd_out(desc_read_cmd_out),
.desc_write_cmd_out(desc_write_cmd_out)
);
endmodule