diff --git a/designs/full_new_reflectometer/tests/full_reflectometer_test/Makefile b/designs/full_new_reflectometer/tests/full_reflectometer_test/Makefile
index ac28f15..0d8703d 100644
--- a/designs/full_new_reflectometer/tests/full_reflectometer_test/Makefile
+++ b/designs/full_new_reflectometer/tests/full_reflectometer_test/Makefile
@@ -7,15 +7,16 @@ PWD := $(shell pwd)
 
 
 RTL_DIR = $(PWD)/../../src
-RTL_ACCUM_DIR = $(PWD)/../../src/accum/src
-RTL_GENERATOR_DIR = $(PWD)/../../src/generator/src
-RTL_SAMPLER_DIR = $(PWD)/../../src/sampler/src
+RTL_ACCUM_DIR = $(PWD)/../../../../rtl/accum/src
+RTL_GENERATOR_DIR = $(PWD)/../../../../rtl/generator/src
+RTL_SAMPLER_DIR = $(PWD)/../../../../rtl/sampler/src
 RTL_CLK_DIR = $(PWD)/../../src/clk_ctrl_wiz/clk_wiz_0
+RTL_CTRL_DIR = $(PWD)/../../../../rtl/controller_new
 LIBS_DIR = $(PWD)/../../../../external/rtl_libs
 
 
 VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_pkg.sv
-VERILOG_SOURCES += $(RTL_DIR)/dma_reg_pkg.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/dma_reg_pkg.sv
 VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_if.sv
 VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axis_if.sv
 VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axis_if_to_flat.sv
@@ -26,14 +27,14 @@ VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_wr.v
 VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma.v
 VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_ram.v
 VERILOG_SOURCES += $(RTL_DIR)/axi_ram_wrapper.sv
-VERILOG_SOURCES += $(RTL_DIR)/controller.sv
-VERILOG_SOURCES += $(RTL_DIR)/dma_controller.sv
-VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_desc.sv
-VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_status.sv
-VERILOG_SOURCES += $(RTL_DIR)/controller_wrapper_axil.sv
-VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller_pkg.sv
-VERILOG_SOURCES += $(RTL_DIR)/axis_defaults_helper.sv
-VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/controller.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/dma_controller.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/shaper_axis_desc.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/shaper_axis_status.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/controller_wrapper_axil.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/axi4l_reg_map_controller_pkg.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/axis_defaults_helper.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/axi4l_reg_map_controller.sv
 VERILOG_SOURCES += $(RTL_DIR)/axi_dma_wrapper_if.sv
 VERILOG_SOURCES += $(RTL_ACCUM_DIR)/adder.sv
 VERILOG_SOURCES += $(RTL_ACCUM_DIR)/out_axis_fifo.sv