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changing the addition of interfaces

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otroubi
2026-07-21 22:37:24 +03:00
parent c121c2c103
commit e06ef3a16b
1 changed files with 42 additions and 5 deletions
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47
designs/controller_dma_connective/src/wrapper_controller_dma.sv
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@ -59,11 +59,49 @@ module wrapper_controller_dma
axi4_if.slave s_axi axi4_if.slave s_axi
); );
axis_if.slave s_axis_status_read; axis_if #(
axis_if.slave s_axis_status_write; .DATA_W($bits(dma_read_status_t)),
.KEEP_W(($bits(dma_read_status_t)+7)/8),
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
) s_axis_status_read (
.aclk(ctrl_clk),
.aresetn(rst_n)
);
axis_if.master m_axis_desc_read; axis_if #(
axis_if.master m_axis_desc_write; .DATA_W($bits(dma_write_status_t)),
.KEEP_W(($bits(dma_write_status_t)+7)/8),
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
) s_axis_status_write (
.aclk(ctrl_clk),
.aresetn(rst_n)
);
axis_if #(
.DATA_W($bits(dma_read_desc_t)),
.KEEP_W(($bits(dma_read_desc_t)+7)/8),
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
) m_axis_desc_read (
.aclk(ctrl_clk),
.aresetn(rst_n)
);
axis_if #(
.DATA_W($bits(dma_write_desc_t)),
.KEEP_W(($bits(dma_write_desc_t)+7)/8),
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
) m_axis_desc_write (
.aclk(ctrl_clk),
.aresetn(rst_n)
);
controller_wrapper_axil controller_wrapper_axil
#( #(
@ -104,7 +142,6 @@ axi_dma_wrapper
#( #(
.AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH), .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_USER_WIDTH(AXI_USER_WIDTH), .AXI_USER_WIDTH(AXI_USER_WIDTH),
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN), .AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),