From ded2afc0dbde38199d5646076f68782b9882c5e1 Mon Sep 17 00:00:00 2001 From: Phil Date: Tue, 31 Mar 2026 12:53:16 +0300 Subject: [PATCH] rtl: add sources for ethernet udp stack --- rtl/ethernet-udp/src/eth/arbi/gmii_arbi.v | 177 +++++ .../src/eth/arbi/gmii_rx_buffer.v | 305 +++++++++ .../src/eth/arbi/gmii_tx_buffer.v | 298 +++++++++ rtl/ethernet-udp/src/eth/mac/arp_cache.v | 51 ++ rtl/ethernet-udp/src/eth/mac/crc.v | 66 ++ rtl/ethernet-udp/src/eth/mac/icmp_reply.v | 558 ++++++++++++++++ rtl/ethernet-udp/src/eth/mac/mac_test.v | 435 ++++++++++++ rtl/ethernet-udp/src/eth/mac/mac_top.v | 176 +++++ rtl/ethernet-udp/src/eth/mac/rx/arp_rx.v | 210 ++++++ rtl/ethernet-udp/src/eth/mac/rx/ip_rx.v | 360 ++++++++++ rtl/ethernet-udp/src/eth/mac/rx/mac_rx.v | 449 +++++++++++++ rtl/ethernet-udp/src/eth/mac/rx/mac_rx_top.v | 186 ++++++ rtl/ethernet-udp/src/eth/mac/rx/udp_rx.v | 372 +++++++++++ rtl/ethernet-udp/src/eth/mac/tx/arp_tx.v | 306 +++++++++ rtl/ethernet-udp/src/eth/mac/tx/ip_tx.v | 400 +++++++++++ rtl/ethernet-udp/src/eth/mac/tx/ip_tx_mode.v | 194 ++++++ rtl/ethernet-udp/src/eth/mac/tx/mac_tx.v | 256 +++++++ rtl/ethernet-udp/src/eth/mac/tx/mac_tx_mode.v | 174 +++++ rtl/ethernet-udp/src/eth/mac/tx/mac_tx_top.v | 258 +++++++ rtl/ethernet-udp/src/eth/mac/tx/udp_tx.v | 631 ++++++++++++++++++ rtl/ethernet-udp/src/eth/reset.v | 20 + rtl/ethernet-udp/src/eth/util_gmii_to_rgmii.v | 253 +++++++ .../src/ip/eth_data_fifo/eth_data_fifo.xci | 461 +++++++++++++ .../icmp_rx_ram_8_256/icmp_rx_ram_8_256.xci | 277 ++++++++ rtl/ethernet-udp/src/ip/len_fifo/len_fifo.xci | 461 +++++++++++++ .../udp_checksum_fifo/udp_checksum_fifo.xci | 461 +++++++++++++ .../udp_rx_ram_8_2048/udp_rx_ram_8_2048.xci | 277 ++++++++ .../ip/udp_tx_data_fifo/udp_tx_data_fifo.xci | 463 +++++++++++++ 28 files changed, 8535 insertions(+) create mode 100644 rtl/ethernet-udp/src/eth/arbi/gmii_arbi.v create mode 100644 rtl/ethernet-udp/src/eth/arbi/gmii_rx_buffer.v create mode 100644 rtl/ethernet-udp/src/eth/arbi/gmii_tx_buffer.v create mode 100644 rtl/ethernet-udp/src/eth/mac/arp_cache.v create mode 100644 rtl/ethernet-udp/src/eth/mac/crc.v create mode 100644 rtl/ethernet-udp/src/eth/mac/icmp_reply.v create mode 100644 rtl/ethernet-udp/src/eth/mac/mac_test.v create mode 100644 rtl/ethernet-udp/src/eth/mac/mac_top.v create mode 100644 rtl/ethernet-udp/src/eth/mac/rx/arp_rx.v create mode 100644 rtl/ethernet-udp/src/eth/mac/rx/ip_rx.v create mode 100644 rtl/ethernet-udp/src/eth/mac/rx/mac_rx.v create mode 100644 rtl/ethernet-udp/src/eth/mac/rx/mac_rx_top.v create mode 100644 rtl/ethernet-udp/src/eth/mac/rx/udp_rx.v create mode 100644 rtl/ethernet-udp/src/eth/mac/tx/arp_tx.v create mode 100644 rtl/ethernet-udp/src/eth/mac/tx/ip_tx.v create mode 100644 rtl/ethernet-udp/src/eth/mac/tx/ip_tx_mode.v create mode 100644 rtl/ethernet-udp/src/eth/mac/tx/mac_tx.v create mode 100644 rtl/ethernet-udp/src/eth/mac/tx/mac_tx_mode.v create mode 100644 rtl/ethernet-udp/src/eth/mac/tx/mac_tx_top.v create mode 100644 rtl/ethernet-udp/src/eth/mac/tx/udp_tx.v create mode 100644 rtl/ethernet-udp/src/eth/reset.v create mode 100644 rtl/ethernet-udp/src/eth/util_gmii_to_rgmii.v create mode 100644 rtl/ethernet-udp/src/ip/eth_data_fifo/eth_data_fifo.xci create mode 100644 rtl/ethernet-udp/src/ip/icmp_rx_ram_8_256/icmp_rx_ram_8_256.xci create mode 100644 rtl/ethernet-udp/src/ip/len_fifo/len_fifo.xci create mode 100644 rtl/ethernet-udp/src/ip/udp_checksum_fifo/udp_checksum_fifo.xci create mode 100644 rtl/ethernet-udp/src/ip/udp_rx_ram_8_2048/udp_rx_ram_8_2048.xci create mode 100644 rtl/ethernet-udp/src/ip/udp_tx_data_fifo/udp_tx_data_fifo.xci diff --git a/rtl/ethernet-udp/src/eth/arbi/gmii_arbi.v b/rtl/ethernet-udp/src/eth/arbi/gmii_arbi.v new file mode 100644 index 0000000..cd855b0 --- /dev/null +++ b/rtl/ethernet-udp/src/eth/arbi/gmii_arbi.v @@ -0,0 +1,177 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Module Name: ethernet_test +////////////////////////////////////////////////////////////////////////////////// +module gmii_arbi +( + input clk, + input rst_n, + input [1:0] speed, + input link, +(* MARK_DEBUG="true" *)input gmii_rx_dv, +(* MARK_DEBUG="true" *)input [7:0] gmii_rxd, +(* MARK_DEBUG="true" *)input gmii_tx_en, +(* MARK_DEBUG="true" *)input [7:0] gmii_txd, +output reg [31:0] pack_total_len, //delay time +output e_rst_n, +(* MARK_DEBUG="true" *)output reg e_rx_dv, +(* MARK_DEBUG="true" *)output reg [7:0] e_rxd, +(* MARK_DEBUG="true" *)output reg e_tx_en, +(* MARK_DEBUG="true" *)output reg [7:0] e_txd +); + +reg eth_1000m_en ; +wire eth_10_100m_en ; +reg eth_100m_en ; +reg eth_10m_en ; +reg [1:0] speed_d0 ; +reg [1:0] speed_d1 ; +reg [1:0] speed_d2 ; +reg link_d0 ; +reg link_d1 ; +reg link_d2 ; + +wire e10_100_tx_en ; +wire [7:0] e10_100_txd ; +wire e10_100_rx_dv ; +wire [7:0] e10_100_rxd ; + +reg e_rst_en ; +reg [7:0] e_rst_cnt ; + +assign e_rst_n = link_d2 & e_rst_en ; + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + speed_d0 <= 2'b00 ; + speed_d1 <= 2'b00 ; + speed_d2 <= 2'b00 ; + link_d0 <= 1'b0 ; + link_d1 <= 1'b0 ; + link_d2 <= 1'b0 ; + end + else + begin + speed_d0 <= speed ; + speed_d1 <= speed_d0 ; + speed_d2 <= speed_d1 ; + link_d0 <= link ; + link_d1 <= link_d0 ; + link_d2 <= link_d1 ; + end + end + + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + eth_1000m_en <= 1'b0 ; + eth_100m_en <= 1'b0 ; + eth_10m_en <= 1'b0 ; + pack_total_len <= 32'd2500000 ; + end + else if (speed_d2 == 2'b10) //1000M + begin + eth_1000m_en <= 1'b1 ; + eth_100m_en <= 1'b0 ; + eth_10m_en <= 1'b0 ; + pack_total_len <= 32'd125000000 ; //1s + end + else if (speed_d2 == 2'b01) //100M + begin + eth_1000m_en <= 1'b0 ; + eth_100m_en <= 1'b1 ; + eth_10m_en <= 1'b0 ; + pack_total_len <= 32'd25000000 ; //1s + end + else if (speed_d2 == 2'b00) //10M + begin + eth_1000m_en <= 1'b0 ; + eth_100m_en <= 1'b0 ; + eth_10m_en <= 1'b1 ; + pack_total_len <= 32'd2500000 ; //1s + end + + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + e_rx_dv <= 1'b0 ; + e_rxd <= 8'd0 ; + e_tx_en <= 1'b0 ; + e_txd <= 8'd0 ; + end + else if (eth_1000m_en) + begin + e_rx_dv <= gmii_rx_dv ; + e_rxd <= gmii_rxd ; + e_tx_en <= gmii_tx_en ; + e_txd <= gmii_txd ; + end + else if (eth_100m_en | eth_10m_en) + begin + e_rx_dv <= e10_100_rx_dv ; + e_rxd <= e10_100_rxd ; + e_tx_en <= e10_100_tx_en ; + e_txd <= e10_100_txd ; + end + end + + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + e_rst_en <= 1'b1 ; + else if (speed_d2 != speed_d1) + e_rst_en <= 1'b0 ; + else if (e_rst_cnt == 8'd200) + e_rst_en <= 1'b1 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + e_rst_cnt <= 8'd0 ; + else if (~e_rst_en) + e_rst_cnt <= e_rst_cnt + 1'b1 ; + else + e_rst_cnt <= 8'd0 ; + end + +assign eth_10_100m_en = eth_100m_en | eth_10m_en ; + +gmii_tx_buffer tx_buffer_inst +( + .clk (clk ), + .rst_n (e_rst_n ), + .eth_10_100m_en (eth_10_100m_en ), + .link (e_rst_n ), + .gmii_tx_en (gmii_tx_en ), + .gmii_txd (gmii_txd ), + .e10_100_tx_en (e10_100_tx_en ), + .e10_100_txd (e10_100_txd ) +); + + +gmii_rx_buffer rx_buffer_inst +( + .clk (clk ), + .rst_n (e_rst_n ), + .link (e_rst_n ), + .eth_100m_en (eth_100m_en ), + .eth_10m_en (eth_10m_en ), + .gmii_rx_dv (gmii_rx_dv ), + .gmii_rxd (gmii_rxd ), + .e10_100_rx_dv (e10_100_rx_dv ), + .e10_100_rxd (e10_100_rxd ) + +); + +endmodule diff --git a/rtl/ethernet-udp/src/eth/arbi/gmii_rx_buffer.v b/rtl/ethernet-udp/src/eth/arbi/gmii_rx_buffer.v new file mode 100644 index 0000000..455dd25 --- /dev/null +++ b/rtl/ethernet-udp/src/eth/arbi/gmii_rx_buffer.v @@ -0,0 +1,305 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Module Name: ethernet_test +////////////////////////////////////////////////////////////////////////////////// +module gmii_rx_buffer +( + input clk, + input rst_n, + input eth_100m_en, //ethernet 100M enable + input eth_10m_en, //ethernet 100M enable + input link, //ethernet link signal + input gmii_rx_dv, //gmii rx dv + input [7:0] gmii_rxd, //gmii rxd + + (* MARK_DEBUG="true" *)output reg e10_100_rx_dv, //ethernet 10/100 rx_dv + (* MARK_DEBUG="true" *)output [7:0] e10_100_rxd //ethernet 10/100 rxd + +); + + +reg [15:0] rx_cnt ; //write fifo counter +reg rx_wren ; //write fifo wren +reg [7:0] rx_wdata ; //write fifo data +reg [15:0] rx_data_cnt ; //read fifo counter +reg rx_rden ; //read fifo rden +wire [7:0] rx_rdata ; //read fifo data +reg [3:0] rxd_high ; //rxd high 4 bit +reg [3:0] rxd_low ; //rxd low 4 bit + +(* MARK_DEBUG="true" *)reg gmii_rx_dv_d0 ; +(* MARK_DEBUG="true" *)reg gmii_rx_dv_d1 ; +reg gmii_rx_dv_d2 ; + +reg [15:0] pack_len ; //package length +reg [1:0] len_cnt ; //length latch counter +wire [4:0] pack_num ; //length fifo usedw +reg rx_len_wren ; //length wren +reg [15:0] rx_len_wdata ; //length write data +reg rx_len_rden ; //length rden +wire [15:0] rx_len ; //legnth read data + + +localparam IDLE = 4'd0 ; +localparam CHECK_FIFO = 4'd1 ; +localparam LEN_LATCH = 4'd2 ; +localparam REC_WAIT = 4'd3 ; +localparam READ_FIFO = 4'd4 ; +localparam REC_END = 4'd5 ; + +reg [3:0] state ; +reg [3:0] next_state ; + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + state <= IDLE ; + else + state <= next_state ; + end + +always @(*) + begin + case(state) + IDLE : + begin + next_state <= CHECK_FIFO ; + end + CHECK_FIFO : + begin + if (pack_num > 5'd0) // if length fifo usedw > 0, means there is package in data fifo + next_state <= LEN_LATCH ; + else + next_state <= CHECK_FIFO ; + end + LEN_LATCH: + begin + if (len_cnt == 2'd3) // delay some clock + next_state <= REC_WAIT ; + else + next_state <= LEN_LATCH ; + end + REC_WAIT : + next_state <= READ_FIFO ; + READ_FIFO : + begin + if (rx_data_cnt == pack_len - 1) // when reach package length read end + next_state <= REC_END ; + else + next_state <= READ_FIFO ; + end + REC_END : + next_state <= IDLE ; + default : + next_state <= IDLE ; + endcase + end + + + + +/************************************************* +write length to fifo +*************************************************/ +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + gmii_rx_dv_d0 <= 1'b0 ; + gmii_rx_dv_d1 <= 1'b0 ; + gmii_rx_dv_d2 <= 1'b0 ; + end + else + begin + gmii_rx_dv_d0 <= gmii_rx_dv ; + gmii_rx_dv_d1 <= gmii_rx_dv_d0 ; + gmii_rx_dv_d2 <= gmii_rx_dv_d1 ; + end + end +//write rx length wren to fifo when gmii_rx_dv negedge +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + rx_len_wren <= 1'b0 ; + else if (gmii_rx_dv == 1'b0 && gmii_rx_dv_d0 == 1'b1) + rx_len_wren <= eth_100m_en | eth_10m_en ; + else + rx_len_wren <= 1'b0 ; +end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + rx_cnt <= 16'd0 ; + //else if (eth_10m_en & (gmii_rx_dv_d0 | gmii_rx_dv_d1)) //when 10M mode, there is one unnecessary 4 bits data need to be take out + else if (eth_10m_en & (gmii_rx_dv | gmii_rx_dv_d0)) //when 10M mode, there is one unnecessary 4 bits data need to be take out + rx_cnt <= rx_cnt + 1'b1 ; + else if (eth_100m_en & (gmii_rx_dv | gmii_rx_dv_d1)) + rx_cnt <= rx_cnt + 1'b1 ; + else if (state == REC_WAIT) + rx_cnt <= 16'd0 ; + end + +//write length to fifo +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + rx_len_wdata <= 16'd0 ; + else + rx_len_wdata <= rx_cnt ; +end + + + +/************************************************* +write data to fifo +*************************************************/ +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + rxd_high <= 4'd0 ; + rxd_low <= 4'd0 ; + end + else if (gmii_rx_dv | gmii_rx_dv_d1) + begin + if (rx_cnt[0]) + begin + rxd_high <= gmii_rxd[3:0] ; + end + else + begin + rxd_low <= gmii_rxd[3:0] ; + end + end + else + begin + rxd_high <= 4'd0 ; + rxd_low <= 4'd0 ; + end + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + rx_wren <= 1'b0 ; + rx_wdata <= 8'd0 ; + end + else if (gmii_rx_dv_d1) + begin + if (rx_cnt[0]) + begin + rx_wren <= 1'b0 ; + end + else + begin + rx_wdata <= {rxd_high,rxd_low} ; + rx_wren <= eth_100m_en | eth_10m_en ; + end + end + else + begin + rx_wren <= 1'b0 ; + rx_wdata <= 8'd0 ; + end + end + +/************************************************* +read length from fifo +*************************************************/ +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + rx_len_rden <= 1'b0 ; + else if (state == LEN_LATCH && len_cnt == 2'd0) + rx_len_rden <= eth_100m_en | eth_10m_en ; + else + rx_len_rden <= 1'b0 ; +end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + len_cnt <= 2'd0 ; + else if (state == LEN_LATCH) + len_cnt <= len_cnt + 1'b1 ; + else + len_cnt <= 2'd0 ; +end +//package total length +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + pack_len <= 16'd0 ; + else if (state == REC_WAIT) + pack_len <= rx_len/2 ; +end + + +/************************************************* +read data from fifo +*************************************************/ + + +//read data counter +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + rx_data_cnt <= 16'd0 ; + else if (state == READ_FIFO) + rx_data_cnt <= rx_data_cnt + 1'b1 ; + else + rx_data_cnt <= 16'd0 ; + end + + +//read enable +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + rx_rden <= 1'b0 ; + else if (state == READ_FIFO) + rx_rden <= eth_100m_en | eth_10m_en ; + else + rx_rden <= 1'b0 ; + end + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + e10_100_rx_dv <= 1'b0 ; + else + e10_100_rx_dv <= rx_rden ; + end + +assign e10_100_rxd = rx_rdata ; + + + eth_data_fifo rx_fifo + ( + .clk (clk ), // input wire clk + .rst (~link ), // input wire rst + .din (rx_wdata ), // input wire [7 : 0] din + .wr_en (rx_wren ), // input wire wr_en + .rd_en (rx_rden ), // input wire rd_en + .dout (rx_rdata ), // output wire [7 : 0] dout + .full ( ), // output wire full + .empty ( ), // output wire empty + .data_count ( ) // output wire [11 : 0] data_count + ); + +len_fifo rx_len_fifo + ( + .clk (clk ), // input wire clk + .rst (~link ), // input wire rst + .din (rx_len_wdata ), // input wire [7 : 0] din + .wr_en (rx_len_wren ), // input wire wr_en + .rd_en (rx_len_rden ), // input wire rd_en + .dout (rx_len ), // output wire [7 : 0] dout + .full ( ), // output wire full + .empty ( ), // output wire empty + .data_count (pack_num ) // output wire [11 : 0] data_count + ); +endmodule diff --git a/rtl/ethernet-udp/src/eth/arbi/gmii_tx_buffer.v b/rtl/ethernet-udp/src/eth/arbi/gmii_tx_buffer.v new file mode 100644 index 0000000..b6e54e0 --- /dev/null +++ b/rtl/ethernet-udp/src/eth/arbi/gmii_tx_buffer.v @@ -0,0 +1,298 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Module Name: ethernet_test +////////////////////////////////////////////////////////////////////////////////// +module gmii_tx_buffer +( + input clk, + input rst_n, + input eth_10_100m_en, //ethernet 10M/100M enable + input link, //ethernet link signal + input gmii_tx_en, //gmii tx enable + input [7:0] gmii_txd, //gmii txd + output reg e10_100_tx_en, //ethernet 10/100M tx enable + output reg [7:0] e10_100_txd //ethernet 10/100M txd + + +); + +(* MARK_DEBUG="true" *)reg [7:0] tx_wdata ; //tx data fifo write data +(* MARK_DEBUG="true" *)reg tx_wren ; //tx data fifo write enable +(* MARK_DEBUG="true" *)reg tx_rden ; //tx data fifo read enable +(* MARK_DEBUG="true" *)reg [15:0] tx_data_cnt ; //tx data counter +(* MARK_DEBUG="true" *)wire [7:0] tx_rdata ; //tx fifo read data + + +reg [16:0] pack_len ; //package length +reg tx_en ; //tx enable +reg [3:0] txd_high ; //high 4 bits +reg [3:0] txd_low ; //low 4 bits + +reg tx_en_d0 ; +reg tx_en_d1 ; + +reg [15:0] tx_len_cnt ; //tx length counter +reg gmii_tx_en_d0 ; +reg [1:0] len_cnt ; //length latch counter +wire [4:0] pack_num ; //length fifo usedw +reg tx_len_wren ; //length fifo wren +reg tx_len_rden ; //length fifo rden +wire [15:0] tx_len_wdata ; //length fifo write data +wire [15:0] tx_len ; //length fifo read data + + + +localparam IDLE = 4'd0 ; +localparam CHECK_FIFO = 4'd1 ; +localparam LEN_LATCH = 4'd2 ; +localparam SEND_WAIT = 4'd3 ; +localparam SEND = 4'd4 ; +localparam SEND_WAIT_1 = 4'd5 ; +localparam SEND_END = 4'd6 ; + + +reg [3:0] state ; +reg [3:0] next_state ; + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + state <= IDLE ; + else + state <= next_state ; + end + + + +always @(*) + begin + case(state) + IDLE : + begin + next_state <= CHECK_FIFO ; + end + CHECK_FIFO : + begin + if (pack_num > 5'd0) //check length fifo, if usedw > 0 ,there is a package in data fifo + next_state <= LEN_LATCH ; + else + next_state <= CHECK_FIFO ; + end + LEN_LATCH: + begin + if (len_cnt == 2'd3) //wait for read length fifo data + next_state <= SEND_WAIT ; + else + next_state <= LEN_LATCH ; + end + SEND_WAIT : + next_state <= SEND ; + SEND : + begin + if (tx_data_cnt == pack_len - 1) //read data fifo and send out + next_state <= SEND_WAIT_1 ; + else + next_state <= SEND ; + end + SEND_WAIT_1 : + begin + if (tx_data_cnt == pack_len + 1) //wait some clock for data latch + next_state <= SEND_END ; + else + next_state <= SEND_WAIT_1 ; + end + SEND_END : + next_state <= IDLE ; + default : + next_state <= IDLE ; + endcase + end +/************************************************* +write length to tx_len_fifo +*************************************************/ +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + gmii_tx_en_d0 <= 1'b0 ; + else + gmii_tx_en_d0 <= gmii_tx_en ; +end +//write tx length to fifo when gmii_tx_en negedge +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + tx_len_wren <= 1'b0 ; + else if (gmii_tx_en == 1'b0 && gmii_tx_en_d0 == 1'b1) + tx_len_wren <= eth_10_100m_en ; + else + tx_len_wren <= 1'b0 ; +end +//calculate tx length +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + tx_len_cnt <= 16'd0 ; + else if (gmii_tx_en) + tx_len_cnt <= tx_len_cnt + 1'b1 ; + else if (tx_len_wren) + tx_len_cnt <= 16'd0 ; +end + +assign tx_len_wdata = tx_len_cnt ; //write length data + +/************************************************* +read length from tx_len_fifo +*************************************************/ +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + tx_len_rden <= 1'b0 ; + else if (state == LEN_LATCH && len_cnt == 2'd0) + tx_len_rden <= eth_10_100m_en ; + else + tx_len_rden <= 1'b0 ; +end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + len_cnt <= 2'd0 ; + else if (state == LEN_LATCH) + len_cnt <= len_cnt + 1'b1 ; + else + len_cnt <= 2'd0 ; +end +//package total length +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + pack_len <= 17'd0 ; + else if (state == SEND_WAIT) + pack_len <= 2*(tx_len) ; +end +//write data to tx_fifo +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + tx_wren <= 1'b0 ; + tx_wdata <= 8'd0 ; + end + else + begin + tx_wren <= gmii_tx_en & eth_10_100m_en ; + tx_wdata <= gmii_txd ; + end + end + +/************************************************* +read tx_fifo +*************************************************/ +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + tx_data_cnt <= 16'd0 ; + else if (state == SEND || state == SEND_WAIT_1) + tx_data_cnt <= tx_data_cnt + 1'b1 ; + else + tx_data_cnt <= 16'd0 ; + end +//read data enable +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + tx_rden <= 1'b0 ; + else if (state == SEND) + tx_rden <= ~tx_data_cnt[0] & eth_10_100m_en ; + else + tx_rden <= 1'b0 ; + end +//gmii tx enable +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + tx_en <= 1'b0 ; + else if (state == SEND) + tx_en <= 1'b1 ; + else + tx_en <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + tx_en_d0 <= 1'b0 ; + tx_en_d1 <= 1'b0 ; + end + else + begin + tx_en_d0 <= tx_en ; + tx_en_d1 <= tx_en_d0 ; + end + end + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + txd_high <= 4'd0 ; + txd_low <= 4'd0 ; + end + else + begin + if (tx_data_cnt[0]) + txd_high <= tx_rdata[7:4] ; + else + txd_low <= tx_rdata[3:0] ; + end + end + +//ethernet 10/100M tx enable +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + e10_100_tx_en <= 1'b0 ; + else + e10_100_tx_en <= tx_en_d1 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + e10_100_txd <= 8'd0 ; + else if (tx_data_cnt[0]) + e10_100_txd <= {txd_low[3:0],txd_low[3:0]} ; + else + e10_100_txd <= {txd_high[3:0],txd_high[3:0]} ; + end + + + eth_data_fifo tx_fifo + ( + .clk (clk ), // input wire clk + .rst (~link ), // input wire rst + .din (tx_wdata ), // input wire [7 : 0] din + .wr_en (tx_wren ), // input wire wr_en + .rd_en (tx_rden ), // input wire rd_en + .dout (tx_rdata ), // output wire [7 : 0] dout + .full ( ), // output wire full + .empty ( ), // output wire empty + .data_count ( ) // output wire [11 : 0] data_count + ); + +len_fifo tx_len_fifo + ( + .clk (clk ), // input wire clk + .rst (~link ), // input wire rst + .din (tx_len_wdata ), // input wire [7 : 0] din + .wr_en (tx_len_wren ), // input wire wr_en + .rd_en (tx_len_rden ), // input wire rd_en + .dout (tx_len ), // output wire [7 : 0] dout + .full ( ), // output wire full + .empty ( ), // output wire empty + .data_count (pack_num ) // output wire [11 : 0] data_count + ); + +endmodule diff --git a/rtl/ethernet-udp/src/eth/mac/arp_cache.v b/rtl/ethernet-udp/src/eth/mac/arp_cache.v new file mode 100644 index 0000000..b9ffb6e --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/arp_cache.v @@ -0,0 +1,51 @@ +module arp_cache +( + input clk , + input rst_n , + + input arp_found, + input [31:0] arp_rec_source_ip_addr, + input [47:0] arp_rec_source_mac_addr, + + input [31:0] destination_ip_addr, + output reg [47:0] destination_mac_addr, + + output reg mac_not_exist +) ; + +reg [79:0] arp_cache ; + +//init arp cache +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_cache <= 80'h00_00_00_00_ff_ff_ff_ff_ff_ff ; + else if (arp_found) + arp_cache <= {arp_rec_source_ip_addr, arp_rec_source_mac_addr} ; + else + arp_cache <= arp_cache ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + destination_mac_addr <= 48'hff_ff_ff_ff_ff_ff ; + else if (destination_ip_addr == arp_cache[79:48]) + destination_mac_addr <= arp_cache[47:0] ; + else + destination_mac_addr <= 48'hff_ff_ff_ff_ff_ff ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + mac_not_exist <= 1'b0 ; + else if (destination_ip_addr != arp_cache[79:48]) + mac_not_exist <= 1'b1 ; + else if (destination_ip_addr == arp_cache[79:48] && arp_cache[47:0] == 48'hff_ff_ff_ff_ff_ff) + mac_not_exist <= 1'b1 ; + else + mac_not_exist <= 1'b0 ; + end + +endmodule diff --git a/rtl/ethernet-udp/src/eth/mac/crc.v b/rtl/ethernet-udp/src/eth/mac/crc.v new file mode 100644 index 0000000..949d48f --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/crc.v @@ -0,0 +1,66 @@ +`timescale 1ns / 1ps +/****************************************/ +// 　CRC32数据校验模块　　　 　　　　// +/****************************************/ +module crc (Clk, Reset, Data_in, Enable, Crc,CrcNext); + + +parameter Tp = 1; + +input Clk; +input Reset; +input [7:0] Data_in; +input Enable; + +output [31:0] Crc; +reg [31:0] Crc; + +output [31:0] CrcNext; + +wire [7:0] Data; + +assign Data={Data_in[0],Data_in[1],Data_in[2],Data_in[3],Data_in[4],Data_in[5],Data_in[6],Data_in[7]}; + + +assign CrcNext[0] = Crc[24] ^ Crc[30] ^ Data[0] ^ Data[6]; +assign CrcNext[1] = Crc[24] ^ Crc[25] ^ Crc[30] ^ Crc[31] ^ Data[0] ^ Data[1] ^ Data[6] ^ Data[7]; +assign CrcNext[2] = Crc[24] ^ Crc[25] ^ Crc[26] ^ Crc[30] ^ Crc[31] ^ Data[0] ^ Data[1] ^ Data[2] ^ Data[6] ^ Data[7]; +assign CrcNext[3] = Crc[25] ^ Crc[26] ^ Crc[27] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[3] ^ Data[7]; +assign CrcNext[4] = Crc[24] ^ Crc[26] ^ Crc[27] ^ Crc[28] ^ Crc[30] ^ Data[0] ^ Data[2] ^ Data[3] ^ Data[4] ^ Data[6]; +assign CrcNext[5] = Crc[24] ^ Crc[25] ^ Crc[27] ^ Crc[28] ^ Crc[29] ^ Crc[30] ^ Crc[31] ^ Data[0] ^ Data[1] ^ Data[3] ^ Data[4] ^ Data[5] ^ Data[6] ^ Data[7]; +assign CrcNext[6] = Crc[25] ^ Crc[26] ^ Crc[28] ^ Crc[29] ^ Crc[30] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[4] ^ Data[5] ^ Data[6] ^ Data[7]; +assign CrcNext[7] = Crc[24] ^ Crc[26] ^ Crc[27] ^ Crc[29] ^ Crc[31] ^ Data[0] ^ Data[2] ^ Data[3] ^ Data[5] ^ Data[7]; +assign CrcNext[8] = Crc[0] ^ Crc[24] ^ Crc[25] ^ Crc[27] ^ Crc[28] ^ Data[0] ^ Data[1] ^ Data[3] ^ Data[4]; +assign CrcNext[9] = Crc[1] ^ Crc[25] ^ Crc[26] ^ Crc[28] ^ Crc[29] ^ Data[1] ^ Data[2] ^ Data[4] ^ Data[5]; +assign CrcNext[10] = Crc[2] ^ Crc[24] ^ Crc[26] ^ Crc[27] ^ Crc[29] ^ Data[0] ^ Data[2] ^ Data[3] ^ Data[5]; +assign CrcNext[11] = Crc[3] ^ Crc[24] ^ Crc[25] ^ Crc[27] ^ Crc[28] ^ Data[0] ^ Data[1] ^ Data[3] ^ Data[4]; +assign CrcNext[12] = Crc[4] ^ Crc[24] ^ Crc[25] ^ Crc[26] ^ Crc[28] ^ Crc[29] ^ Crc[30] ^ Data[0] ^ Data[1] ^ Data[2] ^ Data[4] ^ Data[5] ^ Data[6]; +assign CrcNext[13] = Crc[5] ^ Crc[25] ^ Crc[26] ^ Crc[27] ^ Crc[29] ^ Crc[30] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[3] ^ Data[5] ^ Data[6] ^ Data[7]; +assign CrcNext[14] = Crc[6] ^ Crc[26] ^ Crc[27] ^ Crc[28] ^ Crc[30] ^ Crc[31] ^ Data[2] ^ Data[3] ^ Data[4] ^ Data[6] ^ Data[7]; +assign CrcNext[15] = Crc[7] ^ Crc[27] ^ Crc[28] ^ Crc[29] ^ Crc[31] ^ Data[3] ^ Data[4] ^ Data[5] ^ Data[7]; +assign CrcNext[16] = Crc[8] ^ Crc[24] ^ Crc[28] ^ Crc[29] ^ Data[0] ^ Data[4] ^ Data[5]; +assign CrcNext[17] = Crc[9] ^ Crc[25] ^ Crc[29] ^ Crc[30] ^ Data[1] ^ Data[5] ^ Data[6]; +assign CrcNext[18] = Crc[10] ^ Crc[26] ^ Crc[30] ^ Crc[31] ^ Data[2] ^ Data[6] ^ Data[7]; +assign CrcNext[19] = Crc[11] ^ Crc[27] ^ Crc[31] ^ Data[3] ^ Data[7]; +assign CrcNext[20] = Crc[12] ^ Crc[28] ^ Data[4]; +assign CrcNext[21] = Crc[13] ^ Crc[29] ^ Data[5]; +assign CrcNext[22] = Crc[14] ^ Crc[24] ^ Data[0]; +assign CrcNext[23] = Crc[15] ^ Crc[24] ^ Crc[25] ^ Crc[30] ^ Data[0] ^ Data[1] ^ Data[6]; +assign CrcNext[24] = Crc[16] ^ Crc[25] ^ Crc[26] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[7]; +assign CrcNext[25] = Crc[17] ^ Crc[26] ^ Crc[27] ^ Data[2] ^ Data[3]; +assign CrcNext[26] = Crc[18] ^ Crc[24] ^ Crc[27] ^ Crc[28] ^ Crc[30] ^ Data[0] ^ Data[3] ^ Data[4] ^ Data[6]; +assign CrcNext[27] = Crc[19] ^ Crc[25] ^ Crc[28] ^ Crc[29] ^ Crc[31] ^ Data[1] ^ Data[4] ^ Data[5] ^ Data[7]; +assign CrcNext[28] = Crc[20] ^ Crc[26] ^ Crc[29] ^ Crc[30] ^ Data[2] ^ Data[5] ^ Data[6]; +assign CrcNext[29] = Crc[21] ^ Crc[27] ^ Crc[30] ^ Crc[31] ^ Data[3] ^ Data[6] ^ Data[7]; +assign CrcNext[30] = Crc[22] ^ Crc[28] ^ Crc[31] ^ Data[4] ^ Data[7]; +assign CrcNext[31] = Crc[23] ^ Crc[29] ^ Data[5]; + +always @ (posedge Clk, posedge Reset) + begin + if (Reset) begin + Crc <={32{1'b1}}; + end + else if (Enable) + Crc <=CrcNext; + end +endmodule diff --git a/rtl/ethernet-udp/src/eth/mac/icmp_reply.v b/rtl/ethernet-udp/src/eth/mac/icmp_reply.v new file mode 100644 index 0000000..00300c7 --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/icmp_reply.v @@ -0,0 +1,558 @@ +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : icmp_reply +//Description : This module is used to receive icmp and reply +// + +module icmp_reply +( + input clk, + input rst_n, + + input mac_send_end, + input ip_tx_ack, + input [7:0] icmp_rx_data, //received data + input icmp_rx_req, //receive request + input icmp_rev_error, //receive error from MAC or IP + input [15:0] upper_layer_data_length, //data length received from IP layer + + input icmp_data_req, //IP layer request data + output reg icmp_tx_ready, //icmp reply data ready + output reg [7:0] icmp_tx_data, //icmp reply data + output icmp_tx_end, //icmp reply end + output reg icmp_tx_req //icmp reply request + +); + +localparam ECHO_REQUEST = 8'h08 ; +localparam ECHO_REPLY = 8'h00 ; + +reg [15:0] icmp_rx_cnt ; + +reg icmp_rx_end ; +reg icmp_checksum_error ; //icmp receive checksum error +reg icmp_type_error ; //if icmp type is not 8'h08, do not reply +reg [15:0] icmp_data_length ; //data length register +reg [15:0] icmp_data_length_d0 ; +reg [10:0] icmp_rec_ram_read_addr ; //icmp ram read address +wire [7:0] icmp_rec_ram_rdata ; //icmp ram read data +reg [7:0] icmp_code ; //icmp code +reg [15:0] icmp_id ; //icmp id +reg [15:0] icmp_seq ; //icmp seq +reg checksum_finish ; //icmp reply checksum generated finish + +reg [10:0] ram_write_addr ; //icmp ram write address, when receive icmp, write ram +reg ram_wr_en ; //icmp ram write enable +reg icmp_rev_error_d0 ; + +reg [15:0] timeout ; //timeout counter +reg [7:0] icmp_rx_data_d0 ; //register for receive data + +reg mac_send_end_d0 ; + +//receive and reply FSM +parameter IDLE = 12'b00000_0000_001 ; +parameter REC_DATA = 12'b00000_0000_010 ; +parameter REC_ODD_DATA = 12'b00000_0000_100 ; +parameter VERIFY_CHECKSUM = 12'b00000_0001_000 ; +parameter REC_ERROR = 12'b00000_0010_000 ; +parameter REC_END_WAIT = 12'b00000_0100_000 ; +parameter GEN_CHECKSUM = 12'b00000_1000_000 ; +parameter SEND_WAIT_0 = 12'b00001_0000_000 ; +parameter SEND_WAIT_1 = 12'b00010_0000_000 ; +parameter SEND = 12'b00100_0000_000 ; +parameter REC_END = 12'b01000_0000_000 ; +parameter SEND_END = 12'b10000_0000_000 ; + + + +reg [11:0] state ; +reg [11:0] next_state ; + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + state <= IDLE ; + else + state <= next_state ; + end + +always @(*) + begin + case(state) + IDLE : + begin + if (icmp_rx_req == 1'b1) + next_state <= REC_DATA ; + else + next_state <= IDLE ; + end + REC_DATA : + begin + if (icmp_rev_error_d0 || icmp_type_error) + next_state <= REC_ERROR ; + else if (icmp_data_length[0] == 1'b0 && icmp_rx_cnt == icmp_data_length - 1) + next_state <= VERIFY_CHECKSUM ; + else if (icmp_data_length[0] == 1'b1 && icmp_rx_cnt == icmp_data_length - 2) + next_state <= REC_ODD_DATA ; + else if (icmp_rx_cnt == 16'hffff) + next_state <= IDLE ; + else + next_state <= REC_DATA ; + end + REC_ODD_DATA : + begin + if (icmp_rev_error_d0 || icmp_type_error) + next_state <= REC_ERROR ; + else if (icmp_rx_cnt == icmp_data_length - 1) + next_state <= VERIFY_CHECKSUM ; + else + next_state <= REC_ODD_DATA ; + end + VERIFY_CHECKSUM: + begin + if (icmp_checksum_error) + next_state <= REC_ERROR ; + else if (icmp_rx_end && checksum_finish) + next_state <= REC_END_WAIT ; + else if (icmp_rx_cnt == 16'hffff) + next_state <= IDLE ; + else + next_state <= VERIFY_CHECKSUM ; + end + REC_ERROR : + next_state <= IDLE ; + REC_END_WAIT : + begin + if (icmp_rx_cnt == 16'd63) + next_state <= REC_END ; + else + next_state <= REC_END_WAIT ; + end + SEND_WAIT_0 : + begin + if (ip_tx_ack) + next_state <= SEND_WAIT_1 ; + else + next_state <= SEND_WAIT_0 ; + end + SEND_WAIT_1 : + begin + if (icmp_data_req) + next_state <= SEND ; + else if (timeout == 16'hffff) + next_state <= IDLE ; + else + next_state <= SEND_WAIT_1 ; + end + SEND : + begin + if (icmp_rx_cnt == icmp_data_length) + next_state <= SEND_END ; + else if (icmp_rx_cnt == 16'hffff) + next_state <= IDLE ; + else + next_state <= SEND ; + end + REC_END : + next_state <= SEND_WAIT_0 ; + SEND_END : + begin + if (mac_send_end_d0) + next_state <= IDLE ; + else + next_state <= SEND_END ; + end + default : + next_state <= IDLE ; + endcase + end + + + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + mac_send_end_d0 <= 1'b0 ; + else + mac_send_end_d0 <= mac_send_end ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + icmp_tx_req <= 1'b0 ; + else if (state == SEND_WAIT_1) + icmp_tx_req <= 1'b0 ; + else if (state == REC_END) + icmp_tx_req <= 1'b1 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + icmp_tx_ready <= 1'b0 ; + else if (state == SEND_WAIT_1) + icmp_tx_ready <= 1'b1 ; + else + icmp_tx_ready <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + ram_wr_en <= 1'b0 ; + else if (state == REC_DATA || state == REC_ODD_DATA) + begin + if (icmp_rx_cnt < icmp_data_length && icmp_rx_cnt > 16'd7) + ram_wr_en <= 1'b1 ; + else + ram_wr_en <= 1'b0 ; + end + else + ram_wr_en <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + ram_write_addr <= 11'b0 ; + else if (state == REC_DATA || state == REC_ODD_DATA) + ram_write_addr <= icmp_rx_cnt - 8 ; + else + ram_write_addr <= 11'b0 ; + end + +//timeout counter +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + timeout <= 16'd0 ; + else if (state == SEND_WAIT_1) + timeout <= timeout + 1'b1 ; + else + timeout <= 16'd0 ; + end +//received data register +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + icmp_rx_data_d0 <= 8'd0 ; + else + icmp_rx_data_d0 <= icmp_rx_data ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + icmp_rev_error_d0 <= 1'b0 ; + else + icmp_rev_error_d0 <= icmp_rev_error ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + icmp_data_length <= 16'd0 ; + else if (state == IDLE) + icmp_data_length <= upper_layer_data_length ; + end + + +//icmp receive and reply counter +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + icmp_rx_cnt <= 16'd0 ; + else if (state == REC_DATA || state == REC_END_WAIT || state == SEND) + icmp_rx_cnt <= icmp_rx_cnt + 1'b1 ; + else + icmp_rx_cnt <= 16'd0 ; + end + + +//icmp type is not request +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + icmp_type_error <= 1'b0 ; + else if (state == REC_DATA && icmp_rx_cnt == 16'd0 && icmp_rx_data != ECHO_REQUEST) + icmp_type_error <= 1'b1 ; + else + icmp_type_error <= 1'b0 ; + end + +//icmp code +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + icmp_code <= 8'd0 ; + else if (state == REC_DATA && icmp_rx_cnt == 16'd1) + icmp_code <= icmp_rx_data ; + end + +//icmp id +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + icmp_id <= 16'd0 ; + else if (state == REC_DATA && icmp_rx_cnt == 16'd4) + icmp_id[15:8] <= icmp_rx_data ; + else if (state == REC_DATA && icmp_rx_cnt == 16'd5) + icmp_id[7:0] <= icmp_rx_data ; + end + +//icmp seq +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + icmp_seq <= 16'd0 ; + else if (state == REC_DATA && icmp_rx_cnt == 16'd6) + icmp_seq[15:8] <= icmp_rx_data ; + else if (state == REC_DATA && icmp_rx_cnt == 16'd7) + icmp_seq[7:0] <= icmp_rx_data ; + end + + +//read ram address when reply +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + icmp_rec_ram_read_addr <= 11'd0 ; + else if (state == SEND && icmp_rx_cnt > 5) + icmp_rec_ram_read_addr <= icmp_rx_cnt - 6 ; + else + icmp_rec_ram_read_addr <= 11'd0 ; + end +//received ram: depth 256 width 8 +icmp_rx_ram_8_256 icmp_receive_ram +( + .clka(clk), // input wire clka + .wea(ram_wr_en), // input wire [0 : 0] wea + .addra(ram_write_addr), // input wire [7 : 0] addra + .dina(icmp_rx_data_d0), // input wire [7 : 0] dina + .clkb(clk), // input wire clkb + .addrb(icmp_rec_ram_read_addr), // input wire [7 : 0] addrb + .doutb(icmp_rec_ram_rdata) // output wire [7 : 0] doutb + ); + + +//***************************************************************************// +//verify checksum 32 bit adder, in the end, add itself until high 16 bit is 0 +//** ************************************************************************// +reg [31:0] checksum_tmp ; +reg [31:0] checksum_buf ; +reg [31:0] check_out ; +reg [31:0] checkout_buf ; +wire [15:0] checksum ; +reg [2:0] checksum_cnt ; + +//checksum function +function [31:0] checksum_adder + ( + input [31:0] dataina, + input [31:0] datainb + ); + begin + checksum_adder = dataina + datainb; + end +endfunction + +function [31:0] checksum_out + ( + input [31:0] dataina + ); + begin + checksum_out = dataina[15:0]+dataina[31:16]; + end +endfunction + +always @(posedge clk or negedge rst_n) + begin + if(rst_n == 1'b0) + checksum_tmp <= 32'd0; + else if (state == REC_DATA) + begin + if(icmp_rx_cnt[0] == 1'b1) + checksum_tmp <= checksum_adder({icmp_rx_data_d0,icmp_rx_data},checksum_buf); + end + else if (state == REC_ODD_DATA) + checksum_tmp <= checksum_adder({icmp_rx_data,8'h00},checksum_tmp); //if udp data length is odd, fill with one byte 8'h00 + else if (state == IDLE) + checksum_tmp <= 32'd0; + end + +always @(posedge clk or negedge rst_n) + begin + if(rst_n == 1'b0) + checksum_cnt <= 3'd0 ; + else if (state == VERIFY_CHECKSUM) + checksum_cnt <= checksum_cnt + 1'b1 ; + else + checksum_cnt <= 3'd0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if(rst_n == 1'b0) + check_out <= 32'd0; + else if (state == VERIFY_CHECKSUM) + begin + if (checksum_cnt == 3'd0) + check_out <= checksum_out(checksum_tmp) ; + else if (checksum_cnt == 3'd1) + check_out <= checksum_out(check_out) ; + end + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + checksum_buf <= 32'd0 ; + else if (state == REC_DATA) + checksum_buf <= checksum_tmp ; + else + checksum_buf <= 32'd0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + checkout_buf <= 32'd0 ; + else + checkout_buf <= check_out ; + end + +assign checksum = ~checkout_buf[15:0] ; + +//generate checksum error signal and rx end signal +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + icmp_checksum_error <= 1'b0 ; + icmp_rx_end <= 1'b0 ; + end + else if (state == VERIFY_CHECKSUM && checksum_cnt == 3'd3) + begin + if (checksum == 16'd0) + begin + icmp_checksum_error <= 1'b0 ; + icmp_rx_end <= 1'b1 ; + end + else + begin + icmp_checksum_error <= 1'b1 ; + icmp_rx_end <= 1'b0 ; + end + end + else + begin + icmp_checksum_error <= 1'b0 ; + icmp_rx_end <= 1'b0 ; + end + end + + + +//*******************************************************************// +//reply checksum +//*******************************************************************// +reg [31:0] reply_checksum_tmp ; +reg [31:0] reply_checksum_buf ; +reg [31:0] reply_check_out ; +reg [31:0] reply_checkout_buf ; +wire [15:0] reply_checksum ; + + +always @(posedge clk or negedge rst_n) + begin + if(rst_n == 1'b0) + reply_checksum_tmp <= 32'd0; + else if (state == REC_DATA) + begin + if (icmp_rx_cnt == 16'd1) + reply_checksum_tmp <= checksum_adder({8'h00,icmp_rx_data}, 16'h0000); //source ip address + else if (icmp_rx_cnt == 16'd3) + reply_checksum_tmp <= reply_checksum_tmp ; //source ip address + else + begin + if(icmp_rx_cnt[0] == 1'b1) + reply_checksum_tmp <= checksum_adder({icmp_rx_data_d0,icmp_rx_data},reply_checksum_buf); + end + end + else if (state == REC_ODD_DATA) + reply_checksum_tmp <= checksum_adder({icmp_rx_data,8'h00},reply_checksum_tmp); //if udp data length is odd, fill with one byte 8'h00 + else if (state == IDLE) + reply_checksum_tmp <= 32'd0; + end + + +always @(posedge clk or negedge rst_n) + begin + if(rst_n == 1'b0) + reply_check_out <= 32'd0; + else if (state == VERIFY_CHECKSUM) + begin + if (checksum_cnt == 3'd0) + reply_check_out <= checksum_out(reply_checksum_tmp) ; + else if (checksum_cnt == 3'd1) + reply_check_out <= checksum_out(reply_check_out) ; + end + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + reply_checksum_buf <= 32'd0 ; + else if (state == REC_DATA) + reply_checksum_buf <= reply_checksum_tmp ; + else + reply_checksum_buf <= 32'd0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + reply_checkout_buf <= 32'd0 ; + else if (state == VERIFY_CHECKSUM) + reply_checkout_buf <= reply_check_out ; + end + +assign reply_checksum = ~reply_checkout_buf[15:0] ; + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + checksum_finish <= 1'b0 ; + else if (state == VERIFY_CHECKSUM && checksum_cnt == 3'd3) + checksum_finish <= 1'b1 ; + else + checksum_finish <= 1'b0 ; + end + + +//*****************************************************************************************// +//send icmp data +//*****************************************************************************************// +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + icmp_tx_data <= 8'h00 ; + else if (state == SEND) + begin + case(icmp_rx_cnt) + 16'd0 : icmp_tx_data <= ECHO_REPLY ; + 16'd1 : icmp_tx_data <= icmp_code ; + 16'd2 : icmp_tx_data <= reply_checksum[15:8]; + 16'd3 : icmp_tx_data <= reply_checksum[7:0] ; + 16'd4 : icmp_tx_data <= icmp_id[15:8] ; + 16'd5 : icmp_tx_data <= icmp_id[7:0] ; + 16'd6 : icmp_tx_data <= icmp_seq[15:8] ; + 16'd7 : icmp_tx_data <= icmp_seq[7:0] ; + default : icmp_tx_data <= icmp_rec_ram_rdata ; + endcase + end + else + icmp_tx_data <= 8'h00 ; + end + +endmodule \ No newline at end of file diff --git a/rtl/ethernet-udp/src/eth/mac/mac_test.v b/rtl/ethernet-udp/src/eth/mac/mac_test.v new file mode 100644 index 0000000..1a6ad3a --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/mac_test.v @@ -0,0 +1,435 @@ + +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : mac_top +//Description : +// +////////////////////////////////////////////////////////////////////////////////////// +//`define TEST_SPEED +`timescale 1 ns/1 ns +module mac_test +( + input rst_n , + input [31:0] pack_total_len, + input gmii_tx_clk , + input gmii_rx_clk , + input gmii_rx_dv, + input [7:0] gmii_rxd, + output reg gmii_tx_en, + output reg [7:0] gmii_txd +); + +localparam UDP_WIDTH = 32 ; +localparam UDP_DEPTH = 5 ; + + +reg gmii_rx_dv_d0 ; +reg [7:0] gmii_rxd_d0 ; +wire gmii_tx_en_tmp ; +wire [7:0] gmii_txd_tmp ; + +reg [7:0] ram_wr_data ; +reg ram_wr_en ; +wire udp_ram_data_req ; +reg [15:0] udp_send_data_length ; + +wire [7:0] tx_ram_wr_data ; +wire tx_ram_wr_en ; +wire udp_tx_req ; +wire arp_request_req ; +wire mac_send_end ; +reg write_end ; + +wire [7:0] udp_rec_ram_rdata ; +reg [10:0] udp_rec_ram_read_addr ; +wire [15:0] udp_rec_data_length ; +wire udp_rec_data_valid ; + +wire udp_tx_end ; +wire almost_full ; + +reg udp_ram_wr_en ; +reg udp_write_end ; +wire write_ram_end ; +reg [31:0] wait_cnt ; +reg [UDP_WIDTH-1:0] udp_data [UDP_DEPTH-1:0]; + +reg [4:0] i; +reg [1:0] j ; + +reg write_sel ; + +wire button_negedge ; + +wire mac_not_exist ; +wire arp_found ; + +parameter IDLE = 9'b000_000_001 ; +parameter ARP_REQ = 9'b000_000_010 ; +parameter ARP_SEND = 9'b000_000_100 ; +parameter ARP_WAIT = 9'b000_001_000 ; +parameter GEN_REQ = 9'b000_010_000 ; +parameter WRITE_RAM = 9'b000_100_000 ; +parameter SEND = 9'b001_000_000 ; +parameter WAIT = 9'b010_000_000 ; +parameter CHECK_ARP = 9'b100_000_000 ; + + +reg [8:0] state ; +reg [8:0] next_state ; +reg [15:0] ram_cnt ; +reg almost_full_d0 ; +reg almost_full_d1 ; +always @(posedge gmii_tx_clk or negedge rst_n) + begin + if (~rst_n) + state <= IDLE ; + else + state <= next_state ; + end + +always @(*) + begin + case(state) + IDLE : + begin + if (wait_cnt == pack_total_len) + next_state <= ARP_REQ ; + else + next_state <= IDLE ; + end + + ARP_REQ : + next_state <= ARP_SEND ; + ARP_SEND : + begin + if (mac_send_end) + next_state <= ARP_WAIT ; + else + next_state <= ARP_SEND ; + end + ARP_WAIT : + begin + if (arp_found) + next_state <= WAIT ; + else if (wait_cnt == pack_total_len) + next_state <= ARP_REQ ; + else + next_state <= ARP_WAIT ; + end + GEN_REQ : + begin + if (udp_ram_data_req) + next_state <= WRITE_RAM ; + else + next_state <= GEN_REQ ; + end + WRITE_RAM : + begin + `ifdef TEST_SPEED + if (ram_cnt == udp_send_data_length - 1) + `else + if (write_ram_end) + `endif + next_state <= WAIT ; + else + next_state <= WRITE_RAM ; + end + + SEND : + begin + if (udp_tx_end) + next_state <= WAIT ; + else + next_state <= SEND ; + end + + WAIT : + begin + `ifdef TEST_SPEED + if (wait_cnt == 32'd90) //frame gap + `else + if (wait_cnt == pack_total_len) + `endif + next_state <= CHECK_ARP ; + else + next_state <= WAIT ; + end + CHECK_ARP : + begin + if (mac_not_exist) + next_state <= ARP_REQ ; + else if (almost_full_d1) + next_state <= CHECK_ARP ; + else + next_state <= GEN_REQ ; + end + default : + next_state <= IDLE ; + endcase + end + + +assign write_ram_end = (write_sel)? udp_write_end : write_end ; +assign tx_ram_wr_data = (write_sel)? udp_rec_ram_rdata : ram_wr_data ; +assign tx_ram_wr_en = (write_sel)? udp_ram_wr_en : ram_wr_en ; + + +always@(posedge gmii_rx_clk or negedge rst_n) + begin + if(rst_n == 1'b0) + begin + gmii_rx_dv_d0 <= 1'b0 ; + gmii_rxd_d0 <= 8'd0 ; + end + else + begin + gmii_rx_dv_d0 <= gmii_rx_dv ; + gmii_rxd_d0 <= gmii_rxd ; + end + end + +always@(posedge gmii_tx_clk or negedge rst_n) + begin + if(rst_n == 1'b0) + begin + gmii_tx_en <= 1'b0 ; + gmii_txd <= 8'd0 ; + end + else + begin + gmii_tx_en <= gmii_tx_en_tmp ; + gmii_txd <= gmii_txd_tmp ; + end + end + + + + +mac_top mac_top0 +( + .gmii_tx_clk (gmii_tx_clk) , + .gmii_rx_clk (gmii_rx_clk) , + .rst_n (rst_n) , + + .source_mac_addr (48'h00_0a_35_01_fe_c0) , //source mac address + .TTL (8'h80), + .source_ip_addr (32'hc0a80002), + .destination_ip_addr (32'hc0a80003), + .udp_send_source_port (16'h1f90), + .udp_send_destination_port (16'h1f90), + + .ram_wr_data (tx_ram_wr_data) , + .ram_wr_en (tx_ram_wr_en), + .udp_ram_data_req (udp_ram_data_req), + .udp_send_data_length (udp_send_data_length), + .udp_tx_end (udp_tx_end ), + .almost_full (almost_full ), + + .udp_tx_req (udp_tx_req), + .arp_request_req (arp_request_req ), + + .mac_send_end (mac_send_end), + .mac_data_valid (gmii_tx_en_tmp), + .mac_tx_data (gmii_txd_tmp), + .rx_dv (gmii_rx_dv_d0 ), + .mac_rx_datain (gmii_rxd_d0 ), + + .udp_rec_ram_rdata (udp_rec_ram_rdata), + .udp_rec_ram_read_addr (udp_rec_ram_read_addr), + .udp_rec_data_length (udp_rec_data_length ), + + .udp_rec_data_valid (udp_rec_data_valid), + .arp_found (arp_found ), + .mac_not_exist (mac_not_exist ) +) ; + +always @(*) + begin + udp_data[0] <={"H","E","L","L"}; + udp_data[1] <={"O"," ","A","L"}; + udp_data[2] <={"I","N","X"," "}; + udp_data[3] <={"H","E","I","J"}; + udp_data[4] <={"I","N","\r","\n"}; + + end + +//reg almost_full_d0 ; +//reg almost_full_d1 ; + +always@(posedge gmii_rx_clk or negedge rst_n) + begin + if(rst_n == 1'b0) + begin + almost_full_d0 <= 1'b0 ; + almost_full_d1 <= 1'b0 ; + end + else + begin + almost_full_d0 <= almost_full ; + almost_full_d1 <= almost_full_d0 ; + end + end + +always@(posedge gmii_rx_clk or negedge rst_n) + begin + if(rst_n == 1'b0) + udp_send_data_length <= 16'd0 ; + else if (write_sel) + udp_send_data_length <= udp_rec_data_length - 8 ; + else + `ifdef TEST_SPEED + udp_send_data_length <= 16'd1000 ; + `else + udp_send_data_length <= 4*UDP_DEPTH ; + `endif + end + + +always@(posedge gmii_tx_clk or negedge rst_n) + begin + if(rst_n == 1'b0) + write_sel <= 1'b0 ; + else if (state == WAIT) + begin + if (udp_rec_data_valid) + write_sel <= 1'b1 ; + else + write_sel <= 1'b0 ; + end + end + +assign udp_tx_req = (state == GEN_REQ) ; +assign arp_request_req = (state == ARP_REQ) ; + +always@(posedge gmii_tx_clk or negedge rst_n) + begin + if(rst_n == 1'b0) + wait_cnt <= 0 ; + else if ((state==IDLE||state == WAIT || state == ARP_WAIT) && state != next_state) + wait_cnt <= 0 ; + else if (state==IDLE||state == WAIT || state == ARP_WAIT) + wait_cnt <= wait_cnt + 1'b1 ; + else + wait_cnt <= 0 ; + end + + +`ifdef TEST_SPEED +/*************************************************************/ +//Test ethernet speed +//reg [15:0] ram_cnt ; +always@(posedge gmii_tx_clk or negedge rst_n) + begin + if(rst_n == 1'b0) + ram_cnt <= 11'd0 ; + else if (state == WRITE_RAM) + ram_cnt <= ram_cnt + 1'b1 ; + else + ram_cnt <= 11'd0 ; + end + +always@(posedge gmii_tx_clk or negedge rst_n) + begin + if(rst_n == 1'b0) + ram_wr_en <= 1'b0 ; + else if (state == WRITE_RAM) + ram_wr_en <= 1'b1 ; + else + ram_wr_en <= 1'b0 ; + end + + +always@(posedge gmii_tx_clk or negedge rst_n) + begin + if(rst_n == 1'b0) + ram_wr_data <= 8'd0 ; + else if (state == WRITE_RAM) + ram_wr_data <= ram_cnt[7:0] ; + else + ram_wr_data <= 8'd0 ; + end +/*************************************************************/ +`else +always@(posedge gmii_tx_clk or negedge rst_n) + begin + if(rst_n == 1'b0) + begin + write_end <= 1'b0; + ram_wr_data <= 0; + ram_wr_en <= 0 ; + i <= 0 ; + j <= 0 ; + end + else if (state == WRITE_RAM) + begin + if(i == 5) + begin + ram_wr_en <=1'b0; + write_end <= 1'b1; + end + else + begin + ram_wr_en <= 1'b1 ; + write_end <= 1'b0 ; + j <= j + 1'b1 ; + case(j) + 2'd0 : ram_wr_data <= udp_data[i][31:24] ; + 2'd1 : ram_wr_data <= udp_data[i][23:16] ; + 2'd2 : ram_wr_data <= udp_data[i][15:8] ; + 2'd3 : ram_wr_data <= udp_data[i][7:0] ; + default : ram_wr_data <= 8'h00 ; + endcase + + if (j == 3) + begin + j <= 0 ; + i <= i + 1'b1; + end + end + end + else + begin + write_end <= 1'b0; + ram_wr_data <= 0; + ram_wr_en <= 0 ; + i <= 0 ; + j <= 0 ; + end + end +`endif + +//send udp received data to udp tx ram +always@(posedge gmii_tx_clk or negedge rst_n) + begin + if(rst_n == 1'b0) + udp_rec_ram_read_addr <= 11'd0 ; + else if (state == WRITE_RAM) + udp_rec_ram_read_addr <= udp_rec_ram_read_addr + 1'b1 ; + else + udp_rec_ram_read_addr <= 11'd0 ; + end + +always@(posedge gmii_tx_clk or negedge rst_n) + begin + if(rst_n == 1'b0) + udp_ram_wr_en <= 1'b0 ; + else if (state == WRITE_RAM && udp_rec_ram_read_addr < udp_rec_data_length - 8) + udp_ram_wr_en <= 1'b1 ; + else + udp_ram_wr_en <= 1'b0 ; + end + +always@(posedge gmii_tx_clk or negedge rst_n) + begin + if(rst_n == 1'b0) + udp_write_end <= 1'b0 ; + else if (state == WRITE_RAM && udp_rec_ram_read_addr == udp_rec_data_length - 8) + udp_write_end <= 1'b1 ; + else + udp_write_end <= 1'b0 ; + end + + +endmodule + + diff --git a/rtl/ethernet-udp/src/eth/mac/mac_top.v b/rtl/ethernet-udp/src/eth/mac/mac_top.v new file mode 100644 index 0000000..64e0444 --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/mac_top.v @@ -0,0 +1,176 @@ +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : mac_top +//Description : +// +////////////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ns +module mac_top + ( + input gmii_tx_clk , + input gmii_rx_clk , + input rst_n , + + input [47:0] source_mac_addr , //source mac address + input [7:0] TTL, + input [31:0] source_ip_addr, + input [31:0] destination_ip_addr, + input [15:0] udp_send_source_port, + input [15:0] udp_send_destination_port, + + + input [7:0] ram_wr_data, + input ram_wr_en, + output udp_ram_data_req, + input [15:0] udp_send_data_length, + output udp_tx_end, + output almost_full, + + input udp_tx_req, + input arp_request_req, + output mac_data_valid, + output mac_send_end, + output [7:0] mac_tx_data, + + input rx_dv, + input [7:0] mac_rx_datain, + output [7:0] udp_rec_ram_rdata , + input [10:0] udp_rec_ram_read_addr, + output [15:0] udp_rec_data_length, + output udp_rec_data_valid, + + output arp_found, + output mac_not_exist + + ) ; + + +wire arp_reply_ack ; +wire arp_reply_req ; +wire [31:0] arp_rec_source_ip_addr ; +wire [47:0] arp_rec_source_mac_addr ; +wire [47:0] destination_mac_addr ; + +wire [7:0] mac_rx_dataout ; +wire [15:0] upper_layer_data_length ; +wire icmp_rx_req ; +wire icmp_rev_error ; +wire upper_data_req ; +wire icmp_tx_ready ; +wire [7:0] icmp_tx_data ; +wire icmp_tx_end ; +wire icmp_tx_req ; +wire icmp_tx_ack ; +wire [15:0] icmp_send_data_length ; + +mac_tx_top mac_tx0 + ( + .clk (gmii_tx_clk) , + .rst_n (rst_n) , + + .destination_mac_addr (destination_mac_addr) , //destination mac address + .source_mac_addr (source_mac_addr) , //source mac address + .TTL (TTL), + .source_ip_addr (source_ip_addr), + .destination_ip_addr (destination_ip_addr), + + .udp_send_source_port (udp_send_source_port), + .udp_send_destination_port (udp_send_destination_port), + + .arp_reply_ack (arp_reply_ack ), + .arp_reply_req (arp_reply_req ), + .arp_rec_source_ip_addr (arp_rec_source_ip_addr ), + .arp_rec_source_mac_addr (arp_rec_source_mac_addr ), + .arp_request_req (arp_request_req ), + + + .ram_wr_data (ram_wr_data) , + .ram_wr_en (ram_wr_en), + .udp_tx_req (udp_tx_req), + .udp_send_data_length (udp_send_data_length ), + .udp_ram_data_req (udp_ram_data_req ), + .udp_tx_end (udp_tx_end ), + .almost_full (almost_full ), + + .upper_data_req (upper_data_req ), + .icmp_tx_ready (icmp_tx_ready ), + .icmp_tx_data (icmp_tx_data ), + .icmp_tx_end (icmp_tx_end ), + .icmp_tx_req (icmp_tx_req ), + .icmp_tx_ack (icmp_tx_ack ), + .icmp_send_data_length (icmp_send_data_length), + + .mac_data_valid (mac_data_valid), + .mac_send_end (mac_send_end), + .mac_tx_data (mac_tx_data) + ) ; + + + + + + +mac_rx_top mac_rx0 + ( + .clk (gmii_rx_clk) , + .rst_n (rst_n) , + + .rx_dv (rx_dv ), + .mac_rx_datain (mac_rx_datain ), + + .local_ip_addr (source_ip_addr ), + .local_mac_addr (source_mac_addr), + .arp_reply_ack (arp_reply_ack ), + .arp_reply_req (arp_reply_req ), + .arp_rec_source_ip_addr (arp_rec_source_ip_addr ), + .arp_rec_source_mac_addr (arp_rec_source_mac_addr ), + + .udp_rec_ram_rdata (udp_rec_ram_rdata), + .udp_rec_ram_read_addr (udp_rec_ram_read_addr), + .udp_rec_data_length (udp_rec_data_length ), + .udp_rec_data_valid (udp_rec_data_valid), + + .mac_rx_dataout (mac_rx_dataout ), + .upper_layer_data_length (upper_layer_data_length ), + .ip_total_data_length (icmp_send_data_length), + .icmp_rx_req (icmp_rx_req ), + .icmp_rev_error (icmp_rev_error ), + + .arp_found (arp_found ) + ) ; + + +icmp_reply icmp0 + ( + .clk (gmii_rx_clk) , + .rst_n (rst_n) , + .mac_send_end (mac_send_end ), + .icmp_rx_data (mac_rx_dataout ), + .icmp_rx_req (icmp_rx_req ), + .icmp_rev_error (icmp_rev_error ), + + .upper_layer_data_length (upper_layer_data_length ), + + .icmp_data_req (upper_data_req ), + .icmp_tx_ready (icmp_tx_ready ), + .icmp_tx_data (icmp_tx_data ), + .icmp_tx_end (icmp_tx_end ), + .ip_tx_ack (icmp_tx_ack ), + .icmp_tx_req (icmp_tx_req ) + + + ); + + +arp_cache cache0 +( + .clk (gmii_tx_clk), + .rst_n (rst_n), + .arp_found (arp_found ), + .arp_rec_source_ip_addr (arp_rec_source_ip_addr ), + .arp_rec_source_mac_addr (arp_rec_source_mac_addr ), + .destination_ip_addr (destination_ip_addr), + .destination_mac_addr (destination_mac_addr) , + .mac_not_exist (mac_not_exist ) +); +endmodule + diff --git a/rtl/ethernet-udp/src/eth/mac/rx/arp_rx.v b/rtl/ethernet-udp/src/eth/mac/rx/arp_rx.v new file mode 100644 index 0000000..eb92fa0 --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/rx/arp_rx.v @@ -0,0 +1,210 @@ +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : arp_rx +//Description : This module is used to receive ARP data and send ARP reply request +// +////////////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ns +module arp_rx + ( + input clk, + input rst_n, + input crc_error, + + input [31:0] local_ip_addr, + input [47:0] local_mac_addr, + input [7:0] arp_rx_data, //arp received data + input arp_rx_req, //arp rx request from mac + output reg arp_rx_end, //arp rx end + + input arp_reply_ack, //arp reply ack from arp reply module + output reg arp_reply_req, //arp reply request to arp reply module + + output reg [31:0] arp_rec_source_ip_addr, //arp received source ip address + output reg [47:0] arp_rec_source_mac_addr, //arp received mac address + output reg arp_found //found destination mac address + + ) ; + +localparam ARP_REQUEST_CODE = 16'h0001 ; +localparam ARP_REPLY_CODE = 16'h0002 ; + +reg [31:0] arp_rec_destination_ip_addr ; +reg [47:0] arp_rec_destination_mac_addr ; +reg [15:0] arp_rec_op ; +reg [7:0] arp_rx_cnt ; + +parameter IDLE = 4'b0001 ; +parameter ARP_REC_DATA = 4'b0010 ; +parameter ARP_WAIT = 4'b0100 ; +parameter ARP_END = 4'b1000 ; + +reg [3:0] state ; +reg [3:0] next_state ; + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + state <= IDLE ; + else + state <= next_state ; + end + +always @(*) + begin + case(state) + IDLE : + begin + if (arp_rx_req) + next_state <= ARP_REC_DATA ; + else + next_state <= IDLE ; + end + ARP_REC_DATA : + begin + if (arp_rx_cnt == 45) + next_state <= ARP_WAIT ; + else + next_state <= ARP_REC_DATA ; + end + ARP_WAIT : + begin + if (arp_rx_cnt == 99) + next_state <= ARP_END ; + else + next_state <= ARP_WAIT ; + end + + ARP_END : + next_state <= IDLE ; + + default : + next_state <= IDLE ; + endcase + end + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_rx_end <= 1'b0 ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 44) + arp_rx_end <= 1'b1 ; + else + arp_rx_end <= 1'b0 ; + end + +//received arp request +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_reply_req <= 1'b0 ; + else if (arp_rx_req) + arp_reply_req <= 1'b0 ; + else if (arp_reply_ack) + arp_reply_req <= 1'b0 ; + else if (state == ARP_END && crc_error == 1'b0) + begin + if (arp_rec_op == ARP_REQUEST_CODE && arp_rec_destination_ip_addr == local_ip_addr) + arp_reply_req <= 1'b1 ; + end + end +//received arp reply +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_found <= 1'b0 ; + else if (state == ARP_END && crc_error == 1'b0) + begin + if (arp_rec_op == ARP_REPLY_CODE && arp_rec_destination_ip_addr == local_ip_addr && arp_rec_destination_mac_addr == local_mac_addr) + arp_found <= 1'b1 ; + end + else + arp_found <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_rx_cnt <= 8'd0 ; + else if (state == ARP_REC_DATA || state == ARP_WAIT) + arp_rx_cnt <= arp_rx_cnt + 1'b1 ; + else + arp_rx_cnt <= 8'd0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_rec_op <= 16'd0 ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd6) + arp_rec_op[15:8] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd7) + arp_rec_op[7:0] <= arp_rx_data ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_rec_source_mac_addr <= 48'd0 ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd8) + arp_rec_source_mac_addr[47:40] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd9) + arp_rec_source_mac_addr[39:32] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd10) + arp_rec_source_mac_addr[31:24] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd11) + arp_rec_source_mac_addr[23:16] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd12) + arp_rec_source_mac_addr[15:8] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd13) + arp_rec_source_mac_addr[7:0] <= arp_rx_data ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_rec_source_ip_addr <= 32'd0 ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd14) + arp_rec_source_ip_addr[31:24] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd15) + arp_rec_source_ip_addr[23:16] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd16) + arp_rec_source_ip_addr[15:8] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd17) + arp_rec_source_ip_addr[7:0] <= arp_rx_data ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_rec_destination_mac_addr <= 48'd0 ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd18) + arp_rec_destination_mac_addr[47:40] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd19) + arp_rec_destination_mac_addr[39:32] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd20) + arp_rec_destination_mac_addr[31:24] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd21) + arp_rec_destination_mac_addr[23:16] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd22) + arp_rec_destination_mac_addr[15:8] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd23) + arp_rec_destination_mac_addr[7:0] <= arp_rx_data ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_rec_destination_ip_addr <= 32'd0 ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd24) + arp_rec_destination_ip_addr[31:24] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd25) + arp_rec_destination_ip_addr[23:16] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd26) + arp_rec_destination_ip_addr[15:8] <= arp_rx_data ; + else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd27) + arp_rec_destination_ip_addr[7:0] <= arp_rx_data ; + end + + +endmodule diff --git a/rtl/ethernet-udp/src/eth/mac/rx/ip_rx.v b/rtl/ethernet-udp/src/eth/mac/rx/ip_rx.v new file mode 100644 index 0000000..ce6729c --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/rx/ip_rx.v @@ -0,0 +1,360 @@ +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : ip_rx +//Description : This module is used to receive IP data and verify IP header checksum +// +////////////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ns +module ip_rx +//# +//( +// parameter local_mac_addr = 48'h00_0a_35_01_fe_c0, +// parameter local_ip_addr = 32'hc0a80002 +//) +( + input clk, + input rst_n, + + input [31:0] local_ip_addr, + input [47:0] local_mac_addr, + + input [7:0] ip_rx_data, + input ip_rx_req, + input [47:0] mac_rx_destination_mac_addr, + + output reg udp_rx_req, //udp rx request + output reg icmp_rx_req, //icmp rx request + output reg ip_addr_check_error, //ip address is not equal to local address + + output reg [15:0] upper_layer_data_length, //udp or icmp data length = ip data length - ip header length + output reg [15:0] ip_total_data_length, //send data length + + output reg [7:0] net_protocol, //network layer protocol: 8'h11 udp 8'h01 icmp + output reg [31:0] ip_rec_source_addr, //received source ip address + output reg [31:0] ip_rec_destination_addr, //received destination ip address + + output reg ip_rx_end, + output reg ip_checksum_error + +) ; + +reg [15:0] ip_rx_cnt ; +reg [15:0] ip_rec_data_length ; + +reg [7:0] ip_rx_data_d0 ; +reg [7:0] ip_rx_data_d1 ; + +reg [15:0] ip_rec_checksum ; + +reg [3:0] header_length_buf ; +wire [5:0] header_length ; + +parameter IDLE = 5'b00001 ; +parameter REC_HEADER0 = 5'b00010 ; +parameter REC_HEADER1 = 5'b00100 ; +parameter REC_DATA = 5'b01000 ; +parameter REC_END = 5'b10000 ; + +reg [4:0] state ; +reg [4:0] next_state ; + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + state <= IDLE ; + else + state <= next_state ; +end + +always @(*) +begin + case(state) + IDLE : begin + if (ip_rx_req == 1'b1) + next_state <= REC_HEADER0 ; + else + next_state <= IDLE ; + end + REC_HEADER0 : begin + if (ip_rx_cnt == 16'd3) + next_state <= REC_HEADER1 ; + else + next_state <= REC_HEADER0 ; + end + REC_HEADER1 : begin + if (ip_rx_cnt == header_length - 1) + next_state <= REC_DATA ; + else + next_state <= REC_HEADER1 ; + end + REC_DATA : begin + if (ip_checksum_error || ip_rx_end) + next_state <= REC_END ; + else if (ip_rx_cnt == 16'hffff) + next_state <= REC_END ; + else + next_state <= REC_DATA ; + end + REC_END : next_state <= IDLE ; + default : next_state <= IDLE ; + endcase +end + +assign header_length = 4*header_length_buf ; + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + ip_rx_end <= 1'b0 ; + else if (state == REC_DATA && ip_rx_cnt == ip_total_data_length - 2) + ip_rx_end <= 1'b1 ; + else + ip_rx_end <= 1'b0 ; +end +//mac addr and ip addr is not equal to local addr, assert error +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + ip_addr_check_error <= 1'b0 ; + else if (state == REC_DATA) + begin + if (mac_rx_destination_mac_addr == local_mac_addr && ip_rec_destination_addr == local_ip_addr) + ip_addr_check_error <= 1'b0 ; + else + ip_addr_check_error <= 1'b1 ; + end + else + ip_addr_check_error <= 1'b0 ; +end +//generate udp rx request signal +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + udp_rx_req <= 1'b0 ; + else if (state == REC_HEADER1 && net_protocol == 8'h11 && ip_rx_cnt == header_length - 2) + udp_rx_req <= 1'b1 ; + else + udp_rx_req <= 1'b0 ; +end +//generate icmp rx request signal +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + icmp_rx_req <= 1'b0 ; + else if (state == REC_HEADER1 && net_protocol == 8'h01 && ip_rx_cnt == header_length - 2) + icmp_rx_req <= 1'b1 ; + else + icmp_rx_req <= 1'b0 ; +end + + +//icmp or udp data length +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + begin + upper_layer_data_length <= 16'd0 ; + end + else + begin + upper_layer_data_length <= ip_rec_data_length - header_length ; + end +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + begin + ip_rx_data_d0 <= 8'd0 ; + ip_rx_data_d1 <= 8'd0 ; + end + else + begin + ip_rx_data_d0 <= ip_rx_data ; + ip_rx_data_d1 <= ip_rx_data_d0 ; + end +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + ip_rx_cnt <= 16'd0 ; + else if (state == REC_HEADER0 || state == REC_HEADER1 || state == REC_DATA) + ip_rx_cnt <= ip_rx_cnt + 1'b1 ; + else + ip_rx_cnt <= 16'd0 ; +end +//total length +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + ip_total_data_length <= 16'd0 ; + else if (state == REC_HEADER1) + begin + if (ip_rec_data_length < 16'd46) + ip_total_data_length <= 16'd46 ; + else + ip_total_data_length <= ip_rec_data_length ; + end +end + + +//ip header length +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + header_length_buf <= 4'd0 ; + else if (state == REC_HEADER0 && ip_rx_cnt == 16'd0) + header_length_buf <= ip_rx_data[3:0] ; +end +//ip data total length +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + ip_rec_data_length <= 16'd0 ; + else if (state == REC_HEADER0 && ip_rx_cnt == 16'd2) + ip_rec_data_length[15:8] <= ip_rx_data ; + else if (state == REC_HEADER0 && ip_rx_cnt == 16'd3) + ip_rec_data_length[7:0] <= ip_rx_data ; +end +//network layer protocol +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + net_protocol <= 8'd0 ; + else if (state == REC_HEADER1 && ip_rx_cnt == 16'd9) + net_protocol <= ip_rx_data ; +end + +//ip source address +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + ip_rec_source_addr <= 32'd0 ; + else if (state == REC_HEADER1 && ip_rx_cnt == 16'd12) + ip_rec_source_addr[31:24] <= ip_rx_data ; + else if (state == REC_HEADER1 && ip_rx_cnt == 16'd13) + ip_rec_source_addr[23:16] <= ip_rx_data ; + else if (state == REC_HEADER1 && ip_rx_cnt == 16'd14) + ip_rec_source_addr[15:8] <= ip_rx_data ; + else if (state == REC_HEADER1 && ip_rx_cnt == 16'd15) + ip_rec_source_addr[7:0] <= ip_rx_data ; +end +//ip source address +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + ip_rec_destination_addr <= 32'd0 ; + else if (state == REC_HEADER1 && ip_rx_cnt == 16'd16) + ip_rec_destination_addr[31:24] <= ip_rx_data ; + else if (state == REC_HEADER1 && ip_rx_cnt == 16'd17) + ip_rec_destination_addr[23:16] <= ip_rx_data ; + else if (state == REC_HEADER1 && ip_rx_cnt == 16'd18) + ip_rec_destination_addr[15:8] <= ip_rx_data ; + else if (state == REC_HEADER1 && ip_rx_cnt == 16'd19) + ip_rec_destination_addr[7:0] <= ip_rx_data ; +end + + +//****************************************************************// +//verify checksum +//****************************************************************// +reg [31:0] checksum_tmp ; +reg [31:0] checksum_buf ; +reg [31:0] check_out ; +reg [31:0] checkout_buf ; +wire [15:0] checksum ; +reg [2:0] checksum_cnt ; + +//checksum function +function [31:0] checksum_adder +( + input [31:0] dataina, + input [31:0] datainb +); + +begin + checksum_adder = dataina + datainb; +end +endfunction + +function [31:0] checksum_out +( + input [31:0] dataina +); + +begin + checksum_out = dataina[15:0]+dataina[31:16]; +end + +endfunction + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + checksum_tmp <= 32'd0; + else if (state == REC_HEADER0 || state == REC_HEADER1) + begin + if (ip_rx_cnt[0] == 1'b1) + checksum_tmp <= checksum_adder({ip_rx_data_d0, ip_rx_data},checksum_buf); + end + else if (state == IDLE) + checksum_tmp <= 32'd0; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + check_out <= 32'd0; + else if (state == REC_DATA) + check_out <= checksum_out(checksum_tmp) ; +end + +always @(posedge clk or negedge rst_n) +begin + if(rst_n == 1'b0) + checksum_cnt <= 3'd0 ; + else if (state == REC_DATA) + begin + if (checksum_cnt == 3'd7) + checksum_cnt <= checksum_cnt ; + else + checksum_cnt <= checksum_cnt + 1'b1 ; + end + else + checksum_cnt <= 3'd0 ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + checksum_buf <= 32'd0 ; + else + checksum_buf <= checksum_tmp ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + checkout_buf <= 32'd0 ; + else + checkout_buf <= check_out ; +end + +assign checksum = ~checkout_buf[15:0] ; + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + ip_checksum_error <= 1'b0 ; + else if (state == REC_DATA && checksum_cnt == 3'd2) + begin + if (checksum == 16'd0) + ip_checksum_error <= 1'b0 ; + else + ip_checksum_error <= 1'b1 ; + end + else + ip_checksum_error <= 1'b0 ; +end + +endmodule diff --git a/rtl/ethernet-udp/src/eth/mac/rx/mac_rx.v b/rtl/ethernet-udp/src/eth/mac/rx/mac_rx.v new file mode 100644 index 0000000..25b4a50 --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/rx/mac_rx.v @@ -0,0 +1,449 @@ +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : mac_rx +//Description : This module is used to receive MAC layer data and verify CRC +// +////////////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ns +module mac_rx +( + input clk, + input rst_n, + + input rx_dv, + input [7:0] mac_rx_datain, + + input [31:0] crc_result , + output reg crcen, + output reg crcre, + output reg [7:0] crc_din, + + input checksum_err, //checksum error from IP layer + + input ip_rx_end, //ip receive end + input arp_rx_end, //arp receive end + output reg ip_rx_req, //ip rx request + output reg arp_rx_req, //arp rx request + + output [7:0] mac_rx_dataout, + output reg mac_rec_error , + + output reg [47:0] mac_rx_destination_mac_addr, + output reg [47:0] mac_rx_source_mac_addr +); + +reg [4:0] mac_rx_cnt ; +reg [15:0] mac_crc_cnt ; +reg mac_sync ; //check preamble is right, then sync +reg [63:0] preamble ; +reg [3:0] preamble_cnt ; + +reg [15:0] frame_type ; //type 16'h0800 IP; 16'h0806 ARP + + +wire rx_dv_posedge ; +reg rx_dv_d0 ; +reg rx_dv_d1 ; + +reg [7:0] mac_rx_data_d0 ; +reg [7:0] mac_rx_data_d1 ; +reg [7:0] mac_rx_data_d2 ; + +wire mac_rx_head_end ; + +reg [15:0] timeout ; + +reg [31:0] crc ; +reg [31:0] crc_check ; +reg crc_error ; +reg [31:0] crc_rec ; +reg [31:0] crc_result_d0 ; + +//MAC receive FSM +parameter IDLE = 9'b000_000_001 ; +parameter REC_PREAMBLE = 9'b000_000_010 ; +parameter REC_MAC_HEAD = 9'b000_000_100 ; +parameter REC_IDENTIFY = 9'b000_001_000 ; +parameter REC_IP_DATA = 9'b000_010_000 ; +parameter REC_ARP_DATA = 9'b000_100_000 ; +parameter REC_CRC = 9'b001_000_000 ; +parameter REC_ERROR = 9'b010_000_000 ; +parameter REC_END = 9'b100_000_000 ; + +reg [8:0] rec_state ; +reg [8:0] rec_next_state ; + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + rec_state <= IDLE ; + else + rec_state <= rec_next_state ; +end + +always @(*) +begin + case(rec_state) + IDLE : begin + if (rx_dv_posedge == 1'b1) + rec_next_state <= REC_PREAMBLE ; + else + rec_next_state <= IDLE ; + end + REC_PREAMBLE : begin + if (mac_sync == 1'b1) + rec_next_state <= REC_MAC_HEAD ; + else if (timeout == 16'hffff) + rec_next_state <= REC_ERROR ; + else + rec_next_state <= REC_PREAMBLE ; + end + + REC_MAC_HEAD : begin + if ( mac_rx_cnt == 16'd13) + rec_next_state <= REC_IDENTIFY ; + else if (timeout == 16'hffff) + rec_next_state <= REC_ERROR ; + else + rec_next_state <= REC_MAC_HEAD ; + end + REC_IDENTIFY : begin + if (frame_type == 16'h0800) + rec_next_state <= REC_IP_DATA ; + else if (frame_type == 16'h0806) + rec_next_state <= REC_ARP_DATA ; + else if (timeout == 16'hffff) + rec_next_state <= REC_ERROR ; + else + rec_next_state <= REC_IDENTIFY ; + end + REC_IP_DATA : begin + if (checksum_err) + rec_next_state <= REC_ERROR ; + else if (ip_rx_end) + rec_next_state <= REC_CRC ; + else if (timeout == 16'hffff) + rec_next_state <= REC_ERROR ; + else + rec_next_state <= REC_IP_DATA ; + end + REC_ARP_DATA : begin + if (arp_rx_end) + rec_next_state <= REC_CRC ; + else if (timeout == 16'hffff) + rec_next_state <= REC_ERROR ; + else + rec_next_state <= REC_ARP_DATA ; + end + + REC_CRC : begin + if (crc_error) + rec_next_state <= REC_ERROR ; + else if (mac_rx_cnt == 7) + rec_next_state <= REC_END ; + else + rec_next_state <= REC_CRC ; + end + REC_ERROR : rec_next_state <= IDLE ; + REC_END : rec_next_state <= IDLE ; + default : rec_next_state <= IDLE ; + endcase +end + + + + +assign mac_rx_dataout = mac_rx_data_d2 ; +assign rx_dv_posedge = ~rx_dv_d0 & rx_dv ; + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + begin + crcen <= 1'b0 ; + crcre <= 1'b1 ; + crc_din <= 8'd0 ; + end + else if (rec_state == REC_MAC_HEAD || rec_state == REC_IDENTIFY || rec_state == REC_IP_DATA || rec_state == REC_ARP_DATA) + begin + crcen <= 1'b1 ; + crcre <= 1'b0 ; + crc_din <= mac_rx_data_d0 ; + end + else + begin + crcen <= 1'b0 ; + crcre <= 1'b1 ; + crc_din <= 8'd0 ; + end +end + + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + ip_rx_req <= 1'b0 ; + else if (rec_state == REC_IDENTIFY && frame_type == 16'h0800) + ip_rx_req <= 1'b1 ; + else + ip_rx_req <= 1'b0 ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + arp_rx_req <= 1'b0 ; + else if (rec_state == REC_IDENTIFY && frame_type == 16'h0806) + arp_rx_req <= 1'b1 ; + else + arp_rx_req <= 1'b0 ; +end + +//rx dv and rx data resigster +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + begin + rx_dv_d0 <= 1'b0 ; + rx_dv_d1 <= 1'b0 ; + mac_rx_data_d0 <= 8'd0 ; + mac_rx_data_d1 <= 8'd0 ; + mac_rx_data_d2 <= 8'd0 ; + end + else + begin + rx_dv_d0 <= rx_dv ; + rx_dv_d1 <= rx_dv_d0 ; + mac_rx_data_d0 <= mac_rx_datain ; + mac_rx_data_d1 <= mac_rx_data_d0 ; + mac_rx_data_d2 <= mac_rx_data_d1 ; + end +end +//timeout +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + timeout <= 16'd0 ; + else if (rec_state == REC_PREAMBLE || rec_state == REC_MAC_HEAD || rec_state == REC_MAC_HEAD || rec_state == REC_IDENTIFY + || rec_state == REC_IP_DATA || rec_state == REC_ARP_DATA) + timeout <= timeout + 1'b1 ; + else + timeout <= 16'd0 ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + mac_rx_cnt <= 5'd0 ; + else if (mac_sync) + mac_rx_cnt <= 5'd0 ; + else if (rec_state == REC_PREAMBLE || rec_state == REC_MAC_HEAD || rec_state == REC_CRC) + mac_rx_cnt <= mac_rx_cnt + 1'b1 ; + else + mac_rx_cnt <= 5'd0 ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + mac_crc_cnt <= 16'd0 ; + else if (rx_dv_d1) + mac_crc_cnt <= mac_crc_cnt + 1'b1 ; + else + mac_crc_cnt <= 16'd0 ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + mac_rec_error <= 1'b0 ; + else if (rx_dv_posedge) + mac_rec_error <= 1'b0 ; + else if (rec_state == REC_ERROR) + mac_rec_error <= 1'b1 ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + crc <= 32'd0 ; + else if (crcen) + crc <= crc_result_d0 ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + crc_result_d0 <= 32'd0 ; + else + crc_result_d0 <= crc_result ; +end + + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + crc_check <= 32'd0 ; + else if (rec_state == REC_CRC) + begin + case(mac_rx_cnt) + 5'd1 : crc_check[31:24] <= {~crc[24], ~crc[25], ~crc[26], ~crc[27], ~crc[28], ~crc[29], ~crc[30], ~crc[31]} ; + 5'd2 : crc_check[23:16] <= {~crc[16], ~crc[17], ~crc[18], ~crc[19], ~crc[20], ~crc[21], ~crc[22], ~crc[23]} ; + 5'd3 : crc_check[15:8] <= {~crc[8], ~crc[9], ~crc[10], ~crc[11], ~crc[12], ~crc[13], ~crc[14], ~crc[15]} ; + 5'd4 : crc_check[7:0] <= {~crc[0], ~crc[1], ~crc[2], ~crc[3], ~crc[4], ~crc[5], ~crc[6], ~crc[7]} ; + default : crc_check <= crc_check ; + endcase + end + else + crc_check <= 32'd0 ; +end +//received crc data +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + crc_rec <= 48'd0 ; + else if (rec_state == REC_CRC) + begin + case(mac_rx_cnt) + 5'd0 : crc_rec[31:24] <= mac_rx_data_d2 ; + 5'd1 : crc_rec[23:16] <= mac_rx_data_d2 ; + 5'd2 : crc_rec[15:8] <= mac_rx_data_d2 ; + 5'd3 : crc_rec[7:0] <= mac_rx_data_d2 ; + default : crc_rec <= crc_rec ; + endcase + end + else + crc_rec <= crc_rec ; +end +//check crc +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + crc_error <= 1'b0 ; + else if (rec_state == REC_CRC && mac_rx_cnt == 5) + begin + if (crc_check == crc_rec) + crc_error <= 1'b0 ; + else + crc_error <= 1'b1 ; + end + else + crc_error <= 1'b0 ; +end + +//mac sync signal +always @(*) +begin + if (rec_state == REC_PREAMBLE) + begin + if (mac_rx_cnt == 7 && preamble == 64'h55_55_55_55_55_55_55_d5) + mac_sync <= 1'b1 ; + else + mac_sync <= 1'b0 ; + end + else + mac_sync <= 1'b0 ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + preamble_cnt <= 4'd0 ; + else if (rx_dv) + begin + if (preamble_cnt < 8) + preamble_cnt <= preamble_cnt + 1'b1 ; + end + else + preamble_cnt <= 4'd0 ; +end + + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + preamble <= 64'd0 ; + else if (rx_dv) + begin + if (preamble_cnt == 4'd0) + preamble[63:56] <= mac_rx_datain ; + if (preamble_cnt == 4'd1) + preamble[55:48] <= mac_rx_datain ; + if (preamble_cnt == 4'd2) + preamble[47:40] <= mac_rx_datain ; + if (preamble_cnt == 4'd3) + preamble[39:32] <= mac_rx_datain ; + if (preamble_cnt == 4'd4) + preamble[31:24] <= mac_rx_datain ; + if (preamble_cnt == 4'd5) + preamble[23:16] <= mac_rx_datain ; + if (preamble_cnt == 4'd6) + preamble[15:8] <= mac_rx_datain ; + if (preamble_cnt == 4'd7) + preamble[7:0] <= mac_rx_datain ; + end + else + preamble <= 64'd0 ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + mac_rx_destination_mac_addr <= 48'd0 ; + else if (rec_state == REC_MAC_HEAD) + begin + case(mac_rx_cnt) + 5'd0 : mac_rx_destination_mac_addr[47:40] <= mac_rx_data_d0 ; + 5'd1 : mac_rx_destination_mac_addr[39:32] <= mac_rx_data_d0 ; + 5'd2 : mac_rx_destination_mac_addr[31:24] <= mac_rx_data_d0 ; + 5'd3 : mac_rx_destination_mac_addr[23:16] <= mac_rx_data_d0 ; + 5'd4 : mac_rx_destination_mac_addr[15:8] <= mac_rx_data_d0 ; + 5'd5 : mac_rx_destination_mac_addr[7:0] <= mac_rx_data_d0 ; + default : mac_rx_destination_mac_addr <= mac_rx_destination_mac_addr ; + endcase + end + else + mac_rx_destination_mac_addr <= mac_rx_destination_mac_addr ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + mac_rx_source_mac_addr <= 48'd0 ; + else if (rec_state == REC_MAC_HEAD) + begin + case(mac_rx_cnt) + 5'd6 : mac_rx_source_mac_addr[47:40] <= mac_rx_data_d0 ; + 5'd7 : mac_rx_source_mac_addr[39:32] <= mac_rx_data_d0 ; + 5'd8 : mac_rx_source_mac_addr[31:24] <= mac_rx_data_d0 ; + 5'd9 : mac_rx_source_mac_addr[23:16] <= mac_rx_data_d0 ; + 5'd10 : mac_rx_source_mac_addr[15:8] <= mac_rx_data_d0 ; + 5'd11 : mac_rx_source_mac_addr[7:0] <= mac_rx_data_d0 ; + default : mac_rx_source_mac_addr <= mac_rx_source_mac_addr ; + endcase + end + else + mac_rx_source_mac_addr <= mac_rx_source_mac_addr ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + frame_type <= 16'd0 ; + else if (rec_state == REC_MAC_HEAD) + begin + case(mac_rx_cnt) + 5'd12 : frame_type[15:8] <= mac_rx_data_d0 ; + 5'd13 : frame_type[7:0] <= mac_rx_data_d0 ; + default : frame_type <= frame_type ; + endcase + end + else + frame_type <= frame_type ; +end + + + + +endmodule + + diff --git a/rtl/ethernet-udp/src/eth/mac/rx/mac_rx_top.v b/rtl/ethernet-udp/src/eth/mac/rx/mac_rx_top.v new file mode 100644 index 0000000..017475d --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/rx/mac_rx_top.v @@ -0,0 +1,186 @@ +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : mac_rx_top +//Description : MAC RX Top +// +////////////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ns +module mac_rx_top + ( + input clk, + input rst_n, + + input rx_dv, + input [7:0] mac_rx_datain, + + input [31:0] local_ip_addr, + input [47:0] local_mac_addr, + + input arp_reply_ack, + output arp_reply_req, + output [31:0] arp_rec_source_ip_addr, + output [47:0] arp_rec_source_mac_addr, + + + output [7:0] udp_rec_ram_rdata , + input [10:0] udp_rec_ram_read_addr, + output [15:0] udp_rec_data_length, + output udp_rec_data_valid, + + output [7:0] mac_rx_dataout, + output [15:0] upper_layer_data_length , + output [15:0] ip_total_data_length, + output icmp_rx_req, + output icmp_rev_error, + + output arp_found + ) ; + + + +wire ip_rx_req ; +wire udp_rx_req ; +wire ip_rx_end ; + +wire arp_rx_req ; +wire arp_rx_end ; + +wire [7:0] net_protocol ; +wire [31:0] ip_rec_destination_addr ; +wire [31:0] ip_rec_source_ip_addr ; + +wire ip_addr_check_error ; +wire ip_checksum_error ; +wire mac_rec_error ; + +wire [47:0] mac_rx_destination_mac_addr ; +wire [47:0] mac_rx_source_mac_addr ; + +wire crcen ; +wire crcre ; +wire [7:0] crc_din ; +wire [31:0] crc_result ; + + + +assign icmp_rev_error = (mac_rec_error | ip_checksum_error | ip_addr_check_error) ; + + +crc c0 + ( + .Clk (clk), + .Reset (crcre), + .Data_in (crc_din), + .Enable (crcen), + .Crc (crc_result), + .CrcNext () + ) ; + +mac_rx mac0 + ( + .clk (clk) , + .rst_n (rst_n) , + + .rx_dv (rx_dv ), + .mac_rx_datain (mac_rx_datain ), + + .crc_result (crc_result ) , + .crcen (crcen ), + .crcre (crcre ), + .crc_din (crc_din ), + + .checksum_err (ip_checksum_error ), + + .ip_rx_end (ip_rx_end ), + .arp_rx_end (arp_rx_end), + + .ip_rx_req (ip_rx_req ), + .arp_rx_req (arp_rx_req), + + .mac_rx_dataout (mac_rx_dataout ), + .mac_rec_error (mac_rec_error), + + .mac_rx_destination_mac_addr (mac_rx_destination_mac_addr ), + .mac_rx_source_mac_addr (mac_rx_source_mac_addr) + ); + + +ip_rx ip0 + ( + .clk (clk), + .rst_n (rst_n) , + + .local_ip_addr (local_ip_addr ), + .local_mac_addr (local_mac_addr), + + .ip_rx_data (mac_rx_dataout) , + .ip_rx_req (ip_rx_req) , + .ip_rx_end (ip_rx_end) , + .icmp_rx_req (icmp_rx_req ), + + .ip_addr_check_error (ip_addr_check_error), + .mac_rx_destination_mac_addr (mac_rx_destination_mac_addr), + + .upper_layer_data_length (upper_layer_data_length ), + .ip_total_data_length (ip_total_data_length ), + + .net_protocol (net_protocol), + .ip_rec_source_addr (ip_rec_source_ip_addr), + .ip_rec_destination_addr (ip_rec_destination_addr), + .udp_rx_req (udp_rx_req), + .ip_checksum_error (ip_checksum_error) + + ) ; + + +udp_rx udp0 + ( + .clk (clk) , + .rst_n (rst_n) , + + .udp_rx_data (mac_rx_dataout), + .udp_rx_req (udp_rx_req), + + .mac_rec_error (mac_rec_error), + + .ip_addr_check_error (ip_addr_check_error), + + .net_protocol (net_protocol), + .ip_rec_source_addr (ip_rec_source_ip_addr), + .ip_rec_destination_addr (ip_rec_destination_addr), + .ip_checksum_error (ip_checksum_error), + + .upper_layer_data_length (upper_layer_data_length ), + + .udp_rec_ram_rdata (udp_rec_ram_rdata), + .udp_rec_ram_read_addr (udp_rec_ram_read_addr), + .udp_rec_data_length (udp_rec_data_length ), + + .udp_rec_data_valid (udp_rec_data_valid) + ); + + +arp_rx arp0 + ( + .clk (clk) , + .rst_n (rst_n), + + .crc_error (mac_rec_error), + + .local_ip_addr (local_ip_addr ), + .local_mac_addr (local_mac_addr), + + .arp_rx_data (mac_rx_dataout ), + .arp_rx_req (arp_rx_req ), + + .arp_reply_ack (arp_reply_ack ), + .arp_rx_end (arp_rx_end ), + .arp_reply_req (arp_reply_req ), + + .arp_rec_source_ip_addr (arp_rec_source_ip_addr ), + .arp_rec_source_mac_addr (arp_rec_source_mac_addr ), + .arp_found (arp_found ) + + ) ; + + +endmodule diff --git a/rtl/ethernet-udp/src/eth/mac/rx/udp_rx.v b/rtl/ethernet-udp/src/eth/mac/rx/udp_rx.v new file mode 100644 index 0000000..2ca6c15 --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/rx/udp_rx.v @@ -0,0 +1,372 @@ +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : udp_rx +//Description : This module is used to receive UDP data and verify UDP checksum +// +////////////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ns +module udp_rx +( + input clk, + input rst_n, + + input [7:0] udp_rx_data, + input udp_rx_req, + + input mac_rec_error, + input [7:0] net_protocol, + input [31:0] ip_rec_source_addr, + input [31:0] ip_rec_destination_addr, + input ip_checksum_error, + input ip_addr_check_error, + + input [15:0] upper_layer_data_length, + output [7:0] udp_rec_ram_rdata , //udp ram read data + input [10:0] udp_rec_ram_read_addr, //udp ram read address + output reg [15:0] udp_rec_data_length, //udp data length + output reg udp_rec_data_valid //udp data valid +); + +reg [15:0] udp_rx_cnt ; +reg verify_end ; +reg udp_checksum_error ; + +(* MARK_DEBUG="true" *)reg [10:0] ram_write_addr ; +(* MARK_DEBUG="true" *)reg ram_wr_en ; +reg [15:0] udp_data_length ; +reg ip_addr_check_error_d0 ; +reg [7:0] udp_rx_data_d0 ; //udp data resigster + +parameter IDLE = 8'b0000_0001 ; +parameter REC_HEAD = 8'b0000_0010 ; +parameter REC_DATA = 8'b0000_0100 ; +parameter REC_ODD_DATA = 8'b0000_1000 ; +parameter VERIFY_CHECKSUM = 8'b0001_0000 ; +parameter REC_ERROR = 8'b0010_0000 ; +parameter REC_END_WAIT = 8'b0100_0000 ; +parameter REC_END = 8'b1000_0000 ; + +reg [7:0] state ; +reg [7:0] next_state ; + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + state <= IDLE ; + else + state <= next_state ; +end + +always @(*) +begin + case(state) + IDLE :begin + if (udp_rx_req == 1'b1) + next_state <= REC_HEAD ; + else + next_state <= IDLE ; + end + REC_HEAD : begin + if (ip_checksum_error) + next_state <= REC_ERROR ; + else if (udp_rx_cnt == 16'd7) + begin + if (udp_data_length == 16'd9) + next_state <= REC_ODD_DATA ; + else + next_state <= REC_DATA ; + end + else if (ip_addr_check_error_d0) + next_state <= REC_ERROR ; + else + next_state <= REC_HEAD ; + end + REC_DATA : begin + if (ip_checksum_error) + next_state <= REC_ERROR ; + else if (udp_data_length[0] == 1'b1 && udp_rx_cnt == udp_data_length - 2) + next_state <= REC_ODD_DATA ; + else if (udp_data_length[0] == 1'b0 && udp_rx_cnt == udp_data_length - 1) + next_state <= VERIFY_CHECKSUM ; + else + next_state <= REC_DATA ; + end + REC_ODD_DATA : begin + if (ip_checksum_error) + next_state <= REC_ERROR ; + else if (udp_rx_cnt == udp_data_length - 1) + next_state <= VERIFY_CHECKSUM ; + else + next_state <= REC_ODD_DATA ; + end + VERIFY_CHECKSUM :begin + if (udp_checksum_error) + next_state <= REC_ERROR ; + else if (verify_end) + next_state <= REC_END_WAIT ; + else if (udp_rx_cnt == 16'hffff) + next_state <= IDLE ; + else + next_state <= VERIFY_CHECKSUM ; + end + REC_ERROR : next_state <= IDLE ; + REC_END_WAIT : begin + if (udp_rx_cnt == 16'd63) + next_state <= REC_END ; + else + next_state <= REC_END_WAIT ; + end + REC_END : next_state <= IDLE ; + default : next_state <= IDLE ; + endcase +end + + + + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + ram_wr_en <= 1'b0 ; + else if ((state == REC_DATA || state == REC_ODD_DATA) && udp_rx_cnt < udp_data_length) + ram_wr_en <= 1'b1 ; + else + ram_wr_en <= 1'b0 ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + ram_write_addr <= 11'd0 ; + else if (state == REC_DATA || state == REC_ODD_DATA) + ram_write_addr <= udp_rx_cnt - 8 ; + else + ram_write_addr <= 11'd0 ; +end +//ip address check +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + ip_addr_check_error_d0 <= 1'b0 ; + else + ip_addr_check_error_d0 <= ip_addr_check_error ; +end +//udp data length +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + udp_data_length <= 16'd0 ; + else if (state == IDLE) + udp_data_length <= upper_layer_data_length ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + udp_rec_data_length <= 16'd0 ; + else if (state == REC_END) + udp_rec_data_length <= udp_data_length ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + udp_rx_cnt <= 16'd0 ; + else if (state == REC_HEAD || state == REC_DATA || state == REC_END_WAIT) + udp_rx_cnt <= udp_rx_cnt + 1'b1 ; + else + udp_rx_cnt <= 16'd0 ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + udp_rx_data_d0 <= 8'd0 ; + else + udp_rx_data_d0 <= udp_rx_data ; +end + + +udp_rx_ram_8_2048 udp_receive_ram +( + .clka(clk), // input wire clka + .wea(ram_wr_en), // input wire [0 : 0] wea + .addra(ram_write_addr), // input wire [10 : 0] addra + .dina(udp_rx_data_d0), // input wire [7 : 0] dina + .clkb(clk), // input wire clkb + .addrb(udp_rec_ram_read_addr), // input wire [10 : 0] addrb + .doutb(udp_rec_ram_rdata) // output wire [7 : 0] doutb + ); + +//****************************************************************// +//verify checksum +//****************************************************************// +reg [16:0] checksum_tmp0 ; +reg [16:0] checksum_tmp1 ; +reg [16:0] checksum_tmp2 ; +reg [17:0] checksum_tmp3 ; +reg [18:0] checksum_tmp4 ; +reg [31:0] checksum_tmp5 ; +reg [31:0] checksum_buf ; +reg [31:0] check_out ; +reg [31:0] checkout_buf ; +wire [15:0] checksum ; +reg [2:0] checksum_cnt ; + +//checksum function +function [31:0] checksum_adder +( + input [31:0] dataina, + input [31:0] datainb +); + +begin + checksum_adder = dataina + datainb; +end +endfunction + +function [31:0] checksum_out +( + input [31:0] dataina +); + +begin + checksum_out = dataina[15:0]+dataina[31:16]; +end + +endfunction + +always @(posedge clk or negedge rst_n) +begin + if(rst_n == 1'b0) + begin + checksum_tmp0 <= 17'd0 ; + checksum_tmp1 <= 17'd0 ; + checksum_tmp2 <= 17'd0 ; + checksum_tmp3 <= 18'd0 ; + checksum_tmp4 <= 19'd0 ; + end + else if (state == REC_HEAD) + begin + checksum_tmp0 <= checksum_adder(ip_rec_source_addr[31:16],ip_rec_source_addr[15:0]); //source ip address + checksum_tmp1 <= checksum_adder(ip_rec_destination_addr[31:16],ip_rec_destination_addr[15:0]); //destination ip address + checksum_tmp2 <= checksum_adder({8'd0,net_protocol},udp_data_length); //protocol type + checksum_tmp3 <= checksum_adder(checksum_tmp0,checksum_tmp1); //protocol type + checksum_tmp4 <= checksum_adder(checksum_tmp2,checksum_tmp3); + end + else if (state == IDLE) + begin + checksum_tmp0 <= 17'd0 ; + checksum_tmp1 <= 17'd0 ; + checksum_tmp2 <= 17'd0 ; + checksum_tmp3 <= 18'd0 ; + checksum_tmp4 <= 19'd0 ; + end +end + +always @(posedge clk or negedge rst_n) +begin + if(rst_n == 1'b0) + checksum_tmp5 <= 32'd0; + else if (state == REC_HEAD || state == REC_DATA) + begin + if (udp_rx_cnt[0] == 1'b1) + checksum_tmp5 <= checksum_adder({udp_rx_data_d0,udp_rx_data},checksum_buf); + end + else if (state == REC_ODD_DATA) + checksum_tmp5 <= checksum_adder({udp_rx_data,8'h00},checksum_tmp5); //if udp data length is odd, fill with one byte 8'h00 + else if (state == IDLE) + checksum_tmp5 <= 32'd0 ; +end + +always @(posedge clk or negedge rst_n) +begin + if(rst_n == 1'b0) + checksum_cnt <= 3'd0 ; + else if (state == VERIFY_CHECKSUM) + checksum_cnt <= checksum_cnt + 1'b1 ; + else + checksum_cnt <= 3'd0 ; +end + +always @(posedge clk or negedge rst_n) +begin + if(rst_n == 1'b0) + check_out <= 32'd0; + else if (state == VERIFY_CHECKSUM) + begin + if(checksum_cnt == 3'd0) + check_out <= checksum_adder(checksum_tmp4, checksum_tmp5); + else if (checksum_cnt == 3'd1) + check_out <= checksum_out(check_out) ; + else if (checksum_cnt == 3'd2) + check_out <= checksum_out(check_out) ; + end +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + checksum_buf <= 32'd0 ; + else if (state == REC_HEAD || state == REC_DATA) + checksum_buf <= checksum_tmp5 ; + else + checksum_buf <= 32'd0 ; +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + checkout_buf <= 32'd0 ; + else if (state == VERIFY_CHECKSUM) + checkout_buf <= check_out ; + else + checkout_buf <= 32'd0 ; +end + +assign checksum = ~checkout_buf[15:0] ; +//**************************************************// +//generate udp rx end +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + begin + udp_checksum_error <= 1'b0 ; + verify_end <= 1'b0 ; + end + else if (state == VERIFY_CHECKSUM && checksum_cnt == 3'd4) + begin + if (checksum == 16'd0) + begin + udp_checksum_error <= 1'b0 ; + verify_end <= 1'b1 ; + end + else + begin + udp_checksum_error <= 1'b1 ; + verify_end <= 1'b0 ; + end + end + else + begin + udp_checksum_error <= 1'b0 ; + verify_end <= 1'b0 ; + end +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) + udp_rec_data_valid <= 1'b0 ; + else if (state == REC_END_WAIT) + udp_rec_data_valid <= 1'b0 ; + else if (state == REC_END) + begin + if (mac_rec_error) + udp_rec_data_valid <= 1'b0 ; + else + udp_rec_data_valid <= 1'b1 ; + end +end + + +endmodule diff --git a/rtl/ethernet-udp/src/eth/mac/tx/arp_tx.v b/rtl/ethernet-udp/src/eth/mac/tx/arp_tx.v new file mode 100644 index 0000000..891015e --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/tx/arp_tx.v @@ -0,0 +1,306 @@ +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : arp_tx +//Description : This module is used to send arp data when request arp or reply arp +// +////////////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ns +module arp_tx + ( + input clk , + input rst_n , + + input [47:0] destination_mac_addr , //destination mac address + input [47:0] source_mac_addr , //source mac address + input [31:0] source_ip_addr , //source ip address + input [31:0] destination_ip_addr , //destination ip address + + input mac_data_req, //mac layer request data + input arp_request_req, //arp request + output reg arp_reply_ack, //arp reply ack to arp rx module + input arp_reply_req, //arp reply request from arp rx module + output reg arp_tx_req, + input [31:0] arp_rec_source_ip_addr, + input [47:0] arp_rec_source_mac_addr , + input mac_send_end, + input mac_tx_ack, + + output reg arp_tx_ready, + output reg [7:0] arp_tx_data, + output reg arp_tx_end + ) ; + +localparam mac_type = 16'h0806 ; +localparam hardware_type = 16'h0001 ; +localparam protocol_type = 16'h0800 ; +localparam mac_length = 8'h06 ; +localparam ip_length = 8'h04 ; + +localparam ARP_REQUEST_CODE = 16'h0001 ; +localparam ARP_REPLY_CODE = 16'h0002 ; + + +reg [15:0] op ; + +reg [31:0] arp_destination_ip_addr ; +reg [47:0] arp_destination_mac_addr ; +reg [15:0] arp_send_cnt ; +reg [15:0] timeout ; +reg mac_send_end_d0 ; + +parameter IDLE = 8'b00000001 ; +parameter ARP_REQUEST_WAIT_0 = 8'b00000010 ; +parameter ARP_REQUEST_WAIT_1 = 8'b00000100 ; +parameter ARP_REQUEST = 8'b00001000 ; +parameter ARP_REPLY_WAIT_0 = 8'b00010000 ; +parameter ARP_REPLY_WAIT_1 = 8'b00100000 ; +parameter ARP_REPLY = 8'b01000000 ; +parameter ARP_END = 8'b10000000 ; + +reg [7:0] state ; +reg [7:0] next_state ; + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + state <= IDLE ; + else + state <= next_state ; + end + +always @(*) + begin + case(state) + IDLE : + begin + if (arp_request_req) + next_state <= ARP_REQUEST_WAIT_0 ; + else if (arp_reply_req) + next_state <= ARP_REPLY_WAIT_0 ; + else + next_state <= IDLE ; + end + ARP_REQUEST_WAIT_0 : + begin + if (mac_tx_ack) + next_state <= ARP_REQUEST_WAIT_1 ; + else + next_state <= ARP_REQUEST_WAIT_0 ; + end + ARP_REQUEST_WAIT_1 : + begin + if (mac_data_req) + next_state <= ARP_REQUEST ; + else if (timeout == 16'hffff) + next_state <= IDLE ; + else + next_state <= ARP_REQUEST_WAIT_1 ; + end + ARP_REQUEST : + begin + if (arp_tx_end) + next_state <= ARP_END ; + else + next_state <= ARP_REQUEST ; + end + ARP_REPLY_WAIT_0 : + begin + if (mac_tx_ack) + next_state <= ARP_REPLY_WAIT_1 ; + else + next_state <= ARP_REPLY_WAIT_0 ; + end + ARP_REPLY_WAIT_1 : + begin + if (mac_data_req) + next_state <= ARP_REPLY ; + else if (timeout == 16'hffff) + next_state <= IDLE ; + else + next_state <= ARP_REPLY_WAIT_1 ; + end + ARP_REPLY : + begin + if (arp_tx_end) + next_state <= ARP_END ; + else + next_state <= ARP_REPLY ; + end + ARP_END : + begin + if (mac_send_end_d0) + next_state <= IDLE ; + else + next_state <= ARP_END ; + end + default : + next_state <= IDLE ; + endcase + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + mac_send_end_d0 <= 1'b0 ; + else + mac_send_end_d0 <= mac_send_end ; + end + + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_tx_req <= 1'b0 ; + else if (state == ARP_REQUEST_WAIT_0 || state == ARP_REPLY_WAIT_0) + arp_tx_req <= 1'b1 ; + else + arp_tx_req <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + op <= 16'd0 ; + else if (state == ARP_REPLY) + op <= ARP_REPLY_CODE ; + else + op <= ARP_REQUEST_CODE ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_tx_ready <= 1'b0 ; + else if (state == ARP_REQUEST_WAIT_1 || state == ARP_REPLY_WAIT_1) + arp_tx_ready <= 1'b1 ; + else + arp_tx_ready <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_tx_end <= 1'b0 ; + else if ((state == ARP_REQUEST && arp_send_cnt == 13 + 46 ) || (state == ARP_REPLY && arp_send_cnt == 13 + 46 )) + arp_tx_end <= 1'b1 ; + else + arp_tx_end <= 1'b0 ; + end + + +//timeout counter +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + timeout <= 16'd0 ; + else if (state == ARP_REQUEST_WAIT_1 || state == ARP_REPLY_WAIT_1) + timeout <= timeout + 1'b1 ; + else + timeout <= 16'd0 ; + end + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_destination_ip_addr <= 32'd0 ; + else if (state == ARP_REQUEST_WAIT_1) + arp_destination_ip_addr <= destination_ip_addr ; + else if (state == ARP_REPLY_WAIT_1) + arp_destination_ip_addr <= arp_rec_source_ip_addr ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_destination_mac_addr <= 48'd0 ; + else if (state == ARP_REQUEST_WAIT_1) + arp_destination_mac_addr <= destination_mac_addr ; + else if (state == ARP_REPLY_WAIT_1) + arp_destination_mac_addr <= arp_rec_source_mac_addr ; + end + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_reply_ack <= 1'b0 ; + else if (state == ARP_REPLY_WAIT_1) + arp_reply_ack <= 1'b1 ; + else + arp_reply_ack <= 1'b0 ; + end + + + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_send_cnt <= 16'd0 ; + else if (state == ARP_REQUEST || state == ARP_REPLY) + arp_send_cnt <= arp_send_cnt + 1'b1 ; + else + arp_send_cnt <= 16'd0 ; + end + + + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_tx_data <= 8'd0 ; + else if(state == ARP_REQUEST || state == ARP_REPLY) + begin + case(arp_send_cnt) + 16'd0 : arp_tx_data <= arp_destination_mac_addr[47:40] ; + 16'd1 : arp_tx_data <= arp_destination_mac_addr[39:32] ; + 16'd2 : arp_tx_data <= arp_destination_mac_addr[31:24] ; + 16'd3 : arp_tx_data <= arp_destination_mac_addr[23:16] ; + 16'd4 : arp_tx_data <= arp_destination_mac_addr[15:8] ; + 16'd5 : arp_tx_data <= arp_destination_mac_addr[7:0] ; + 16'd6 : arp_tx_data <= source_mac_addr[47:40] ; + 16'd7 : arp_tx_data <= source_mac_addr[39:32] ; + 16'd8 : arp_tx_data <= source_mac_addr[31:24] ; + 16'd9 : arp_tx_data <= source_mac_addr[23:16] ; + 16'd10 : arp_tx_data <= source_mac_addr[15:8] ; + 16'd11 : arp_tx_data <= source_mac_addr[7:0] ; + 16'd12 : arp_tx_data <= mac_type[15:8] ; //frame type + 16'd13 : arp_tx_data <= mac_type[7:0] ; + 16'd14 : arp_tx_data <= hardware_type[15:8] ; //hardware type + 16'd15 : arp_tx_data <= hardware_type[7:0] ; + 16'd16 : arp_tx_data <= protocol_type[15:8] ; //protocol type using IP 0800 + 16'd17 : arp_tx_data <= protocol_type[7:0] ; + 16'd18 : arp_tx_data <= mac_length ; //MAC address length + 16'd19 : arp_tx_data <= ip_length ; //IP address length + 16'd20 : arp_tx_data <= op[15:8] ; + 16'd21 : arp_tx_data <= op[7:0] ; + 16'd22 : arp_tx_data <= source_mac_addr[47:40] ; + 16'd23 : arp_tx_data <= source_mac_addr[39:32] ; + 16'd24 : arp_tx_data <= source_mac_addr[31:24] ; + 16'd25 : arp_tx_data <= source_mac_addr[23:16] ; + 16'd26 : arp_tx_data <= source_mac_addr[15:8] ; + 16'd27 : arp_tx_data <= source_mac_addr[7:0] ; + 16'd28 : arp_tx_data <= source_ip_addr[31:24] ; + 16'd29 : arp_tx_data <= source_ip_addr[23:16] ; + 16'd30 : arp_tx_data <= source_ip_addr[15:8] ; + 16'd31 : arp_tx_data <= source_ip_addr[7:0] ; + 16'd32 : arp_tx_data <= arp_destination_mac_addr[47:40] ; + 16'd33 : arp_tx_data <= arp_destination_mac_addr[39:32] ; + 16'd34 : arp_tx_data <= arp_destination_mac_addr[31:24] ; + 16'd35 : arp_tx_data <= arp_destination_mac_addr[23:16] ; + 16'd36 : arp_tx_data <= arp_destination_mac_addr[15:8] ; + 16'd37 : arp_tx_data <= arp_destination_mac_addr[7:0] ; + 16'd38 : arp_tx_data <= arp_destination_ip_addr[31:24] ; + 16'd39 : arp_tx_data <= arp_destination_ip_addr[23:16] ; + 16'd40 : arp_tx_data <= arp_destination_ip_addr[15:8] ; + 16'd41 : arp_tx_data <= arp_destination_ip_addr[7:0] ; + default : arp_tx_data <= 8'd0 ; + endcase + end + else + arp_tx_data <= 8'd0 ; + end + + + +endmodule diff --git a/rtl/ethernet-udp/src/eth/mac/tx/ip_tx.v b/rtl/ethernet-udp/src/eth/mac/tx/ip_tx.v new file mode 100644 index 0000000..3a9a6d7 --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/tx/ip_tx.v @@ -0,0 +1,400 @@ +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : ip_tx +//Description : This module is used to send ip layer data, generate ip header checksum, +// receive data from udp or icmp, then send to mac layer +// +// +////////////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ns +module ip_tx + ( + input clk , + input rst_n , + + input [47:0] destination_mac_addr , //destination mac address + input [47:0] source_mac_addr , //source mac address + input [7:0] TTL, + input [7:0] ip_send_type, + input [31:0] source_ip_addr, + input [31:0] destination_ip_addr, + input [7:0] upper_layer_data, //data from udp or icmp + output reg upper_data_req, //request data from udp or icmp + + input mac_tx_ack, + input mac_send_end, + input mac_data_req, + input upper_tx_ready, + input ip_tx_req, + input [15:0] ip_send_data_length , + + output reg ip_tx_ack, + output ip_tx_busy, + output reg ip_tx_ready, + output reg [7:0] ip_tx_data, + output reg ip_tx_end + ) ; + +localparam mac_type = 16'h0800 ; +localparam ip_version = 4'h4 ; //ipv4 +localparam header_len = 4'h5 ; //header length + +reg checksum_finish ; +reg [15:0] identify_code ; +reg [15:0] ip_send_data_length_d0 ; +reg [15:0] ip_send_cnt ; +reg [15:0] timeout ; +reg [3:0] wait_cnt ; +reg mac_send_end_d0 ; + +parameter IDLE = 8'b0000_0001 ; +parameter START = 8'b0000_0010 ; +parameter WAIT_DATA_LENGTH = 8'b0000_0100 ; +parameter GEN_CHECKSUM = 8'b0000_1000 ; +parameter SEND_WAIT = 8'b0001_0000 ; +parameter WAIT_MAC = 8'b0010_0000 ; +parameter IP_SEND = 8'b0100_0000 ; +parameter IP_END = 8'b1000_0000 ; + +reg [7:0] state ; +reg [7:0] next_state ; + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + state <= IDLE ; + else + state <= next_state ; + end + +always @(*) + begin + case(state) + IDLE : + begin + if (ip_tx_req) + next_state <= START ; + else + next_state <= IDLE ; + end + START : + begin + if (mac_tx_ack) + next_state <= WAIT_DATA_LENGTH ; + else + next_state <= START ; + end + WAIT_DATA_LENGTH : + begin + if (wait_cnt == 4'd7) + next_state <= GEN_CHECKSUM ; + else + next_state <= WAIT_DATA_LENGTH ; + end + GEN_CHECKSUM : + begin + if (checksum_finish) + next_state <= SEND_WAIT ; + else + next_state <= GEN_CHECKSUM ; + end + + SEND_WAIT : + begin + if (upper_tx_ready) + next_state <= WAIT_MAC ; + else if (timeout == 16'hffff) + next_state <= IDLE ; + else + next_state <= SEND_WAIT ; + end + WAIT_MAC : + begin + if (mac_data_req) + next_state <= IP_SEND ; + else if (timeout == 16'hffff) + next_state <= IDLE ; + else + next_state <= WAIT_MAC ; + end + IP_SEND : + begin + if (ip_send_cnt == 14 + ip_send_data_length_d0) + next_state <= IP_END ; + else + next_state <= IP_SEND ; + end + IP_END : + begin + if (mac_send_end_d0) + next_state <= IDLE ; + else + next_state <= IP_END ; + end + default : + next_state <= IDLE ; + endcase + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + mac_send_end_d0 <= 1'b0 ; + else + mac_send_end_d0 <= mac_send_end ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + ip_tx_ack <= 1'b0 ; + else if (state == WAIT_DATA_LENGTH) + ip_tx_ack <= 1'b1 ; + else + ip_tx_ack <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + ip_tx_ready <= 1'b0 ; + else if (state == WAIT_MAC) + ip_tx_ready <= upper_tx_ready ; + else + ip_tx_ready <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + ip_tx_end <= 1'b0 ; + else if ((state == IP_SEND) && (ip_send_cnt == 13 + ip_send_data_length_d0)) + ip_tx_end <= 1'b1 ; + else + ip_tx_end <= 1'b0 ; + end + +//request data from icmp or udp +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + upper_data_req <= 1'b0 ; + else if (state == IP_SEND && ip_send_cnt == 16'd30) + upper_data_req <= 1'b1 ; + else + upper_data_req <= 1'b0 ; + end + +//timeout counter +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + timeout <= 16'd0 ; + else if (upper_tx_ready) + timeout <= 16'd0 ; + else if (state == SEND_WAIT || state == WAIT_MAC) + timeout <= timeout + 1'b1 ; + else + timeout <= 16'd0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + wait_cnt <= 4'd0 ; + else if (state == WAIT_DATA_LENGTH) + wait_cnt <= wait_cnt + 1'b1 ; + else + wait_cnt <= 4'd0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + identify_code <= 16'd0 ; + else if (ip_tx_end) + identify_code <= identify_code + 1'b1 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + ip_send_data_length_d0 <= 16'd0 ; + else + begin + if (ip_send_data_length < 46) + ip_send_data_length_d0 <= 16'd46 ; + else + ip_send_data_length_d0 <= ip_send_data_length ; + end + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + ip_send_cnt <= 16'd0 ; + else if (state == GEN_CHECKSUM || state == IP_SEND) + ip_send_cnt <= ip_send_cnt + 1'b1 ; + else + ip_send_cnt <= 16'd0 ; + end +//checksum generation + +reg [16:0] checksum_tmp0 ; +reg [16:0] checksum_tmp1 ; +reg [16:0] checksum_tmp2 ; +reg [16:0] checksum_tmp3 ; +reg [16:0] checksum_tmp4 ; +reg [17:0] checksum_tmp5 ; +reg [17:0] checksum_tmp6 ; +reg [18:0] checksum_tmp7 ; +reg [19:0] checksum_tmp8 ; +reg [19:0] check_out ; +reg [19:0] checkout_buf ; +reg [15:0] checksum ; + + +//checksum function +function [31:0] checksum_adder + ( + input [31:0] dataina, + input [31:0] datainb + ); + + begin + checksum_adder = dataina + datainb; + end +endfunction + +function [31:0] checksum_out + ( + input [31:0] dataina + ); + + begin + checksum_out = dataina[15:0]+dataina[31:16]; + end + +endfunction + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + checksum_tmp0 <= 17'd0 ; + checksum_tmp1 <= 17'd0 ; + checksum_tmp2 <= 17'd0 ; + checksum_tmp3 <= 17'd0 ; + checksum_tmp4 <= 17'd0 ; + checksum_tmp5 <= 18'd0 ; + checksum_tmp6 <= 18'd0 ; + checksum_tmp7 <= 19'd0 ; + checksum_tmp8 <= 20'd0 ; + check_out <= 20'd0 ; + checkout_buf <= 20'd0 ; + end + else if (state == GEN_CHECKSUM) + begin + checksum_tmp0 <= checksum_adder(16'h4500,ip_send_data_length); + checksum_tmp1 <= checksum_adder(identify_code, 16'h4000) ; + checksum_tmp2 <= checksum_adder({TTL,ip_send_type}, 16'h0000) ; + checksum_tmp3 <= checksum_adder(source_ip_addr[31:16], source_ip_addr[15:0]) ; + checksum_tmp4 <= checksum_adder(destination_ip_addr[31:16], destination_ip_addr[15:0]) ; + checksum_tmp5 <= checksum_adder(checksum_tmp0, checksum_tmp1) ; + checksum_tmp6 <= checksum_adder(checksum_tmp2, checksum_tmp3) ; + checksum_tmp7 <= checksum_adder(checksum_tmp5, checksum_tmp6) ; + checksum_tmp8 <= checksum_adder(checksum_tmp4, checksum_tmp7) ; + check_out <= checksum_out(checksum_tmp8) ; + checkout_buf <= checksum_out(check_out) ; + end + else if (state == IDLE) + begin + checksum_tmp0 <= 17'd0 ; + checksum_tmp1 <= 17'd0 ; + checksum_tmp2 <= 17'd0 ; + checksum_tmp3 <= 17'd0 ; + checksum_tmp4 <= 17'd0 ; + checksum_tmp5 <= 18'd0 ; + checksum_tmp6 <= 18'd0 ; + checksum_tmp7 <= 19'd0 ; + checksum_tmp8 <= 20'd0 ; + check_out <= 20'd0 ; + checkout_buf <= 20'd0 ; + end + end + + + + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + checksum <= 32'd0 ; + else if (state == GEN_CHECKSUM) + checksum <= ~checkout_buf[15:0] ; + end +//assign checksum = ~checkout_buf[15:0] ; +//*******************************************************// + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + checksum_finish <= 1'b0 ; + else if (state == GEN_CHECKSUM && ip_send_cnt == 16'd13) + checksum_finish <= 1'b1 ; + else + checksum_finish <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + ip_tx_data <= 8'h00 ; + else if (state == IP_SEND) + begin + case(ip_send_cnt) + 16'd0 : ip_tx_data <= destination_mac_addr[47:40] ; + 16'd1 : ip_tx_data <= destination_mac_addr[39:32] ; + 16'd2 : ip_tx_data <= destination_mac_addr[31:24] ; + 16'd3 : ip_tx_data <= destination_mac_addr[23:16] ; + 16'd4 : ip_tx_data <= destination_mac_addr[15:8] ; + 16'd5 : ip_tx_data <= destination_mac_addr[7:0] ; + 16'd6 : ip_tx_data <= source_mac_addr[47:40] ; + 16'd7 : ip_tx_data <= source_mac_addr[39:32] ; + 16'd8 : ip_tx_data <= source_mac_addr[31:24] ; + 16'd9 : ip_tx_data <= source_mac_addr[23:16] ; + 16'd10 : ip_tx_data <= source_mac_addr[15:8] ; + 16'd11 : ip_tx_data <= source_mac_addr[7:0] ; + 16'd12 : ip_tx_data <= mac_type[15:8] ; + 16'd13 : ip_tx_data <= mac_type[7:0] ; + 16'd14 : ip_tx_data <= {ip_version, header_len} ; + 16'd15 : ip_tx_data <= 8'h00 ; + 16'd16 : ip_tx_data <= ip_send_data_length[15:8] ; + 16'd17 : ip_tx_data <= ip_send_data_length[7:0] ; + 16'd18 : ip_tx_data <= identify_code[15:8] ; + 16'd19 : ip_tx_data <= identify_code[7:0] ; + 16'd20 : ip_tx_data <= 8'h40 ; + 16'd21 : ip_tx_data <= 8'h00 ; + 16'd22 : ip_tx_data <= TTL ; + 16'd23 : ip_tx_data <= ip_send_type ; + 16'd24 : ip_tx_data <= checksum[15:8] ; + 16'd25 : ip_tx_data <= checksum[7:0] ; + 16'd26 : ip_tx_data <= source_ip_addr[31:24] ; + 16'd27 : ip_tx_data <= source_ip_addr[23:16] ; + 16'd28 : ip_tx_data <= source_ip_addr[15:8] ; + 16'd29 : ip_tx_data <= source_ip_addr[7:0] ; + 16'd30 : ip_tx_data <= destination_ip_addr[31:24] ; + 16'd31 : ip_tx_data <= destination_ip_addr[23:16] ; + 16'd32 : ip_tx_data <= destination_ip_addr[15:8] ; + 16'd33 : ip_tx_data <= destination_ip_addr[7:0] ; + default : ip_tx_data <= upper_layer_data ; + endcase + end + else + ip_tx_data <= 8'h00 ; + end + + + +endmodule diff --git a/rtl/ethernet-udp/src/eth/mac/tx/ip_tx_mode.v b/rtl/ethernet-udp/src/eth/mac/tx/ip_tx_mode.v new file mode 100644 index 0000000..8860f3c --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/tx/ip_tx_mode.v @@ -0,0 +1,194 @@ +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : ip_tx_mode +//Description : This module is arbitration for ip layer signal, which from udp and icmp +// +////////////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ns +module ip_tx_mode + ( + input clk , + input rst_n, + input mac_send_end, + + + input udp_tx_req, + input udp_tx_ready , + input [7:0] udp_tx_data, + input [15:0] udp_send_data_length, + output reg udp_tx_ack, + + input icmp_tx_req, + input icmp_tx_ready, + input [7:0] icmp_tx_data, + input [15:0] icmp_send_data_length, + output reg icmp_tx_ack, + + input ip_tx_ack, + output reg ip_tx_req, + output reg ip_tx_ready, + output reg [7:0] ip_tx_data, + output reg [7:0] ip_send_type, + output reg [15:0] ip_send_data_length + + + ); + +localparam ip_udp_type = 8'h11 ; +localparam ip_icmp_type = 8'h01 ; + +reg [15:0] timeout ; + +parameter IDLE = 5'b00001 ; +parameter UDP_WAIT = 5'b00010 ; +parameter UDP = 5'b00100 ; +parameter ICMP_WAIT = 5'b01000 ; +parameter ICMP = 5'b10000 ; + + +reg [4:0] state ; +reg [4:0] next_state ; + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + state <= IDLE ; + else + state <= next_state ; + end + +always @(*) + begin + case(state) + IDLE : + begin + if (udp_tx_req) + next_state <= UDP_WAIT ; + else if (icmp_tx_req) + next_state <= ICMP_WAIT ; + else + next_state <= IDLE ; + end + UDP_WAIT : + begin + if (ip_tx_ack) + next_state <= UDP ; + else + next_state <= UDP_WAIT ; + end + UDP : + begin + if (mac_send_end) + next_state <= IDLE ; + else if (timeout == 16'hffff) + next_state <= IDLE ; + else + next_state <= UDP ; + end + ICMP_WAIT : + begin + if (ip_tx_ack) + next_state <= ICMP ; + else + next_state <= ICMP_WAIT ; + end + ICMP : + begin + if (mac_send_end) + next_state <= IDLE ; + else if (timeout == 16'hffff) + next_state <= IDLE ; + else + next_state <= ICMP ; + end + default : + next_state <= IDLE ; + endcase + end + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + timeout <= 16'd0 ; + else if (state == UDP || state == ICMP) + timeout <= timeout + 1'b1 ; + else + timeout <= 16'd0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + ip_send_data_length <= 16'd0 ; + else if (state == ICMP_WAIT || state == ICMP) + ip_send_data_length <= icmp_send_data_length ; + else + ip_send_data_length <= udp_send_data_length + 28 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + ip_tx_req <= 1'b0 ; + else if (state == UDP_WAIT || state == ICMP_WAIT) + ip_tx_req <= 1'b1 ; + else + ip_tx_req <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + udp_tx_ack <= 1'b0 ; + else if (state == UDP) + udp_tx_ack <= 1'b1 ; + else + udp_tx_ack <= 1'b0 ; + end + + + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + icmp_tx_ack <= 1'b0 ; + else if (state == ICMP) + icmp_tx_ack <= 1'b1 ; + else + icmp_tx_ack <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + ip_tx_ready <= 1'b0 ; + ip_tx_data <= 8'h00 ; + ip_send_type <= ip_udp_type ; + end + else if (state == UDP) + begin + ip_tx_ready <= udp_tx_ready ; + ip_tx_data <= udp_tx_data ; + ip_send_type <= ip_udp_type ; + + end + else if (state == ICMP) + begin + ip_tx_ready <= icmp_tx_ready ; + ip_tx_data <= icmp_tx_data ; + ip_send_type <= ip_icmp_type ; + + end + else + begin + ip_tx_ready <= 1'b0 ; + ip_tx_data <= 8'h00 ; + ip_send_type <= ip_udp_type ; + end + end + + + +endmodule + + diff --git a/rtl/ethernet-udp/src/eth/mac/tx/mac_tx.v b/rtl/ethernet-udp/src/eth/mac/tx/mac_tx.v new file mode 100644 index 0000000..e131d19 --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/tx/mac_tx.v @@ -0,0 +1,256 @@ +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : mac_tx +//Description : This module is MAC layer module, which receive data from ARP or IP module, +// In this module, CRC checksum is generated +// +////////////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ns +module mac_tx + ( + input clk, + input rst_n, + + input [31:0] crc_result , + output reg crcen, + output reg crcre, + output reg [7:0] crc_din, + + input mac_tx_req, + input [7:0] mac_frame_data, //data from ip or arp + input mac_tx_ready, //ready from ip or arp + input mac_tx_end, //end from ip or arp + + output reg mac_tx_ack, + output reg [7:0] mac_tx_data, + output reg mac_send_end, + output reg mac_data_valid, + output reg mac_data_req //request data from arp or ip + + ) ; + + +reg [3:0] mac_tx_cnt ; +reg [31:0] crc ; + +reg [7:0] mac_frame_data_dly ; +reg mac_tx_end_dly ; +reg [7:0] mac_tx_data_tmp ; +reg mac_data_valid_tmp ; +reg [15:0] timeout ; + + +//MAC send FSM +parameter SEND_IDLE = 6'b000_001 ; +parameter SEND_START = 6'b000_010 ; +parameter SEND_PREAMBLE = 6'b000_100 ; +parameter SEND_DATA = 6'b001_000 ; +parameter SEND_CRC = 6'b010_000 ; +parameter SEND_END = 6'b100_000 ; + +reg [5:0] send_state ; +reg [5:0] send_next_state ; + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + send_state <= SEND_START ; + else + send_state <= send_next_state ; + end + +always @(*) + begin + case(send_state) + SEND_IDLE : + begin + if (mac_tx_req) + send_next_state <= SEND_START ; + else + send_next_state <= SEND_IDLE ; + end + SEND_START : + begin + if (mac_tx_ready) + send_next_state <= SEND_PREAMBLE ; + else + send_next_state <= SEND_START ; + end + SEND_PREAMBLE : + begin + if (mac_tx_cnt == 7) + send_next_state <= SEND_DATA ; + else + send_next_state <= SEND_PREAMBLE ; + end + SEND_DATA : + begin + if (mac_tx_end_dly) + send_next_state <= SEND_CRC ; + else if (timeout == 16'hffff) + send_next_state <= SEND_END ; + else + send_next_state <= SEND_DATA ; + end + SEND_CRC : + begin + if (mac_tx_cnt == 4) + send_next_state <= SEND_END ; + else + send_next_state <= SEND_CRC ; + end + SEND_END : + send_next_state <= SEND_IDLE ; + default : + send_next_state <= SEND_IDLE ; + endcase + end + + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + mac_tx_ack <= 1'b0 ; + else if (send_state == SEND_START) + mac_tx_ack <= 1'b1 ; + else + mac_tx_ack <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + mac_send_end <= 1'b0 ; + else if (send_state == SEND_END) + mac_send_end <= 1'b1 ; + else + mac_send_end <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + crcre <= 1'b1 ; + crcen <= 1'b0 ; + crc_din <= 8'd0 ; + end + else if (send_state == SEND_DATA || (send_state == SEND_PREAMBLE && mac_tx_cnt == 7)) + begin + crcre <= 1'b0 ; + crcen <= 1'b1 ; + crc_din <= mac_frame_data ; + end + else + begin + crcre <= 1'b1 ; + crcen <= 1'b0 ; + crc_din <= 8'd0 ; + end + end + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + mac_data_valid_tmp <= 1'b0 ; + else if (send_state == SEND_PREAMBLE || send_state == SEND_DATA || (send_state == SEND_CRC && mac_tx_cnt < 4)) + mac_data_valid_tmp <= 1'b1 ; + else + mac_data_valid_tmp <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + mac_data_valid <= 1'b0 ; + else + mac_data_valid <= mac_data_valid_tmp ; + end +//request data from arp or ip +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + mac_data_req <= 1'b0 ; + else if (send_state == SEND_PREAMBLE && mac_tx_cnt == 3) + mac_data_req <= 1'b1 ; + else + mac_data_req <= 1'b0 ; + end +//timeout counter +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + timeout <= 16'd0 ; + else if (send_state == SEND_DATA) + timeout <= timeout + 1'b1 ; + else + timeout <= 16'd0 ; + end + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + crc <= 32'hffffffff ; + else if (crcen) + crc <= crc_result ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + mac_frame_data_dly <= 8'd0 ; + mac_tx_end_dly <= 1'b0 ; + end + else + begin + mac_frame_data_dly <= mac_frame_data ; + mac_tx_end_dly <= mac_tx_end ; + end + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + mac_tx_cnt <= 4'd0 ; + else if (send_state == SEND_PREAMBLE || send_state == SEND_CRC) + mac_tx_cnt <= mac_tx_cnt + 1'b1 ; + else + mac_tx_cnt <= 4'd0 ; + end +//mac send data frame +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + mac_tx_data_tmp <= 8'h00 ; + else if (send_state == SEND_PREAMBLE) + begin + if (mac_tx_cnt < 7) + mac_tx_data_tmp <= 8'h55 ; + else + mac_tx_data_tmp <= 8'hd5 ; + end + else if (send_state == SEND_DATA) + mac_tx_data_tmp <= mac_frame_data_dly ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + mac_tx_data <= 8'h00 ; + else if (send_state == SEND_CRC) + begin + case(mac_tx_cnt) + 4'd0 : mac_tx_data <= mac_tx_data_tmp ; + 4'd1 : mac_tx_data <= {~crc[24], ~crc[25], ~crc[26], ~crc[27], ~crc[28], ~crc[29], ~crc[30], ~crc[31]} ; + 4'd2 : mac_tx_data <= {~crc[16], ~crc[17], ~crc[18], ~crc[19], ~crc[20], ~crc[21], ~crc[22], ~crc[23]} ; + 4'd3 : mac_tx_data <= {~crc[8], ~crc[9], ~crc[10], ~crc[11], ~crc[12], ~crc[13], ~crc[14], ~crc[15]} ; + 4'd4 : mac_tx_data <= {~crc[0], ~crc[1], ~crc[2], ~crc[3], ~crc[4], ~crc[5], ~crc[6], ~crc[7]} ; + default : mac_tx_data <= 8'h00 ; + endcase + end + else + mac_tx_data <= mac_tx_data_tmp ; + end + +endmodule diff --git a/rtl/ethernet-udp/src/eth/mac/tx/mac_tx_mode.v b/rtl/ethernet-udp/src/eth/mac/tx/mac_tx_mode.v new file mode 100644 index 0000000..b5fba81 --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/tx/mac_tx_mode.v @@ -0,0 +1,174 @@ +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : mac_tx_mode +//Description : This module is arbitration for MAC layer signal, which from IP and ARP +// +////////////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ns +module mac_tx_mode + ( + input clk , + input rst_n, + input mac_send_end, + + input arp_tx_req, + input arp_tx_ready , + input [7:0] arp_tx_data, + input arp_tx_end, + output reg arp_tx_ack, + + input ip_tx_req, + input ip_tx_ready, + input [7:0] ip_tx_data, + input ip_tx_end, + output reg ip_tx_ack, + + input mac_tx_ack, + output reg mac_tx_req, + output reg mac_tx_ready, + output reg [7:0] mac_tx_data, + output reg mac_tx_end + ); + + + +reg [15:0] timeout ; + +parameter IDLE = 5'b00001 ; +parameter ARP_WAIT = 5'b00010 ; +parameter ARP = 5'b00100 ; +parameter IP_WAIT = 5'b01000 ; +parameter IP = 5'b10000 ; + + +reg [4:0] state ; +reg [4:0] next_state ; + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + state <= IDLE ; + else + state <= next_state ; + end + +always @(*) + begin + case(state) + IDLE : + begin + if (arp_tx_req) + next_state <= ARP_WAIT ; + else if (ip_tx_req) + next_state <= IP_WAIT ; + else + next_state <= IDLE ; + end + ARP_WAIT : + begin + if (mac_tx_ack) + next_state <= ARP ; + else + next_state <= IP ; + end + ARP : + begin + if (mac_send_end) + next_state <= IDLE ; + else if (timeout == 16'hffff) + next_state <= IDLE ; + else + next_state <= ARP ; + end + IP_WAIT : + begin + if (mac_tx_ack) + next_state <= IP ; + else + next_state <= IP_WAIT ; + end + IP : + begin + if (mac_send_end) + next_state <= IDLE ; + else if (timeout == 16'hffff) + next_state <= IDLE ; + else + next_state <= IP ; + end + default : + next_state <= IDLE ; + endcase + end + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + timeout <= 16'd0 ; + else if (state == ARP || state == IP) + timeout <= timeout + 1'b1 ; + else + timeout <= 16'd0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + arp_tx_ack <= 1'b0 ; + else if (state == ARP) + arp_tx_ack <= 1'b1 ; + else + arp_tx_ack <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + ip_tx_ack <= 1'b0 ; + else if (state == IP) + ip_tx_ack <= 1'b1 ; + else + ip_tx_ack <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + mac_tx_req <= 1'b0 ; + else if (state == ARP_WAIT || state == IP_WAIT) + mac_tx_req <= 1'b1 ; + else + mac_tx_req <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + begin + mac_tx_ready <= 1'b0 ; + mac_tx_data <= 8'h00 ; + mac_tx_end <= 1'b0 ; + end + else if (state == ARP) + begin + mac_tx_ready <= arp_tx_ready ; + mac_tx_data <= arp_tx_data ; + mac_tx_end <= arp_tx_end ; + end + else if (state == IP) + begin + mac_tx_ready <= ip_tx_ready ; + mac_tx_data <= ip_tx_data ; + mac_tx_end <= ip_tx_end ; + end + else + begin + mac_tx_ready <= 1'b0 ; + mac_tx_data <= 8'h00 ; + mac_tx_end <= 1'b0 ; + end + end + +endmodule + + diff --git a/rtl/ethernet-udp/src/eth/mac/tx/mac_tx_top.v b/rtl/ethernet-udp/src/eth/mac/tx/mac_tx_top.v new file mode 100644 index 0000000..71457af --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/tx/mac_tx_top.v @@ -0,0 +1,258 @@ +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : mac_tx_top +//Description : MAC TX Top module +// +////////////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ns +module mac_tx_top + ( + input clk , + input rst_n , + + input [47:0] destination_mac_addr , //destination mac address + input [47:0] source_mac_addr , //source mac address + input [7:0] TTL, + input [31:0] source_ip_addr, + input [31:0] destination_ip_addr, + input [15:0] udp_send_source_port, + input [15:0] udp_send_destination_port, + + output arp_reply_ack, + input arp_reply_req, + input [31:0] arp_rec_source_ip_addr, + input [47:0] arp_rec_source_mac_addr, + input arp_request_req, + + + input [7:0] ram_wr_data, + input ram_wr_en, + input udp_tx_req, + output udp_ram_data_req, + input [15:0] udp_send_data_length, + output udp_tx_end, + output almost_full, + + output upper_data_req, + input icmp_tx_ready, + input [7:0] icmp_tx_data, + input icmp_tx_end, + input icmp_tx_req, + output icmp_tx_ack, + input [15:0] icmp_send_data_length, + + output mac_data_valid, + output mac_send_end, + output [7:0] mac_tx_data + ) ; + + +wire crcen ; +wire crcre ; +wire [7:0] crc_din ; +wire [31:0] crc_result ; + +wire mac_data_req ; +wire [7:0] mac_frame_data ; +wire mac_tx_ready ; +wire mac_tx_end ; + +wire ip_tx_ready ; +wire [7:0] ip_tx_data ; +wire ip_tx_end ; + +wire arp_tx_ready ; +wire [7:0] arp_tx_data ; +wire arp_tx_end ; + + +wire [15:0] ip_send_data_length ; + + +wire [7:0] udp_tx_data ; +wire udp_data_req ; +wire udp_tx_ready ; +wire udp_tx_req_tmp ; + +wire upper_tx_ready ; +wire [7:0] upper_layer_data ; + + + + +wire [7:0] ip_send_type ; + + +wire arp_tx_req ; +wire arp_tx_ack ; +wire ip_tx_req ; +wire ip_tx_ack ; +wire mac_tx_ack ; +wire mac_tx_req ; +wire mac_ip_tx_ack ; +wire mac_arp_tx_ack ; + +wire udp_tx_ack; +mac_tx mac0 + ( + .clk (clk ), + .rst_n (rst_n ), + + .crc_result (crc_result ), + .crcen (crcen ), + .crcre (crcre ), + .crc_din (crc_din ), + + .mac_tx_req (mac_tx_req ), + .mac_frame_data (mac_frame_data ), + .mac_tx_ready (mac_tx_ready ), + .mac_tx_end (mac_tx_end ) , + + .mac_tx_ack (mac_tx_ack ), + .mac_tx_data (mac_tx_data ), + .mac_send_end (mac_send_end ), + .mac_data_valid (mac_data_valid ), + .mac_data_req (mac_data_req ) + + ) ; + +mac_tx_mode mode0 + ( + .clk (clk ), + .rst_n (rst_n ), + .mac_send_end (mac_send_end ), + + .arp_tx_req (arp_tx_req ), + .arp_tx_ready (arp_tx_ready ), + .arp_tx_data (arp_tx_data ), + .arp_tx_end (arp_tx_end ), + .arp_tx_ack (mac_arp_tx_ack ), + + .ip_tx_req (ip_tx_req ), + .ip_tx_ready (ip_tx_ready ), + .ip_tx_data (ip_tx_data ), + .ip_tx_end (ip_tx_end ), + .ip_tx_ack (mac_ip_tx_ack ), + + .mac_tx_ack (mac_tx_ack ), + .mac_tx_req (mac_tx_req ), + .mac_tx_ready (mac_tx_ready ), + .mac_tx_data (mac_frame_data ), + .mac_tx_end (mac_tx_end ) + ); + +crc c0 + ( + .Clk (clk ), + .Reset (crcre ), + .Data_in (crc_din ), + .Enable (crcen ), + .Crc (crc_result ), + .CrcNext ( ) + ) ; + +arp_tx arp_tx0 + ( + .clk (clk ) , + .rst_n (rst_n ) , + + .destination_mac_addr (destination_mac_addr ) , //destination mac address + .source_mac_addr (source_mac_addr ) , //source mac address + .source_ip_addr (source_ip_addr ) , //source ip address + .destination_ip_addr (destination_ip_addr ) , //destination ip address + + .mac_data_req (mac_data_req ) , + .mac_send_end (mac_send_end ), + + .mac_tx_ack (mac_arp_tx_ack ), + .arp_tx_req (arp_tx_req ), + .arp_request_req (arp_request_req ) , //arp request + .arp_reply_ack (arp_reply_ack ), + .arp_reply_req (arp_reply_req ), + .arp_rec_source_ip_addr (arp_rec_source_ip_addr ), + .arp_rec_source_mac_addr (arp_rec_source_mac_addr ), + .arp_tx_ready (arp_tx_ready ) , + .arp_tx_data (arp_tx_data ) , + .arp_tx_end (arp_tx_end ) + ) ; + + +ip_tx ip0 + ( + .clk (clk ), + .rst_n (rst_n ), + .destination_mac_addr (destination_mac_addr ), //destination mac address + .source_mac_addr (source_mac_addr ), //source mac address + .ip_send_data_length (ip_send_data_length ), + .TTL (TTL ), + .ip_send_type (ip_send_type ), + .source_ip_addr (source_ip_addr ), + .destination_ip_addr (destination_ip_addr ), + .upper_layer_data (upper_layer_data ), + .upper_data_req (upper_data_req ), + .upper_tx_ready (upper_tx_ready ), + + .mac_data_req (mac_data_req ), + .mac_send_end (mac_send_end ), + .mac_tx_ack (mac_ip_tx_ack ), + + .ip_tx_req (ip_tx_req ), + .ip_tx_ack (ip_tx_ack ), + .ip_tx_ready (ip_tx_ready ), + .ip_tx_data (ip_tx_data ), + .ip_tx_end (ip_tx_end ) + + ) ; + +ip_tx_mode ipmode + ( + .clk (clk ), + .rst_n (rst_n ), + .mac_send_end (mac_send_end ), + + .udp_tx_req (udp_tx_req_tmp ), + .udp_tx_ack (udp_tx_ack ), + .udp_tx_ready (udp_tx_ready ), + .udp_tx_data (udp_tx_data ), + .udp_send_data_length (udp_send_data_length ), + + .icmp_tx_req (icmp_tx_req ), + .icmp_tx_ack (icmp_tx_ack ), + .icmp_tx_ready (icmp_tx_ready ), + .icmp_tx_data (icmp_tx_data ), + .icmp_send_data_length (icmp_send_data_length ), + + .ip_tx_req (ip_tx_req ), + .ip_tx_ack (ip_tx_ack ), + .ip_tx_ready (upper_tx_ready ), + .ip_tx_data (upper_layer_data ), + .ip_send_type (ip_send_type ), + .ip_send_data_length (ip_send_data_length ) + + + ); + +udp_tx udp0 + ( + .clk (clk ), + .rst_n (rst_n ), + .source_ip_addr (source_ip_addr ), + .destination_ip_addr (destination_ip_addr ), + .udp_send_source_port (udp_send_source_port ), + .udp_send_destination_port (udp_send_destination_port ), + .udp_send_data_length (udp_send_data_length ), + .udp_ram_data_req (udp_ram_data_req ), + .mac_send_end (mac_send_end ), + .ip_tx_req (udp_tx_req_tmp ), + .ip_tx_ack (udp_tx_ack ), + .ram_wr_data (ram_wr_data ), + .ram_wr_en (ram_wr_en ), + .udp_tx_req (udp_tx_req ), + .udp_data_req (upper_data_req ), + .udp_tx_ready (udp_tx_ready ), + .udp_tx_data (udp_tx_data ), + .udp_tx_end (udp_tx_end ), + .almost_full (almost_full ) + ) ; + +endmodule + diff --git a/rtl/ethernet-udp/src/eth/mac/tx/udp_tx.v b/rtl/ethernet-udp/src/eth/mac/tx/udp_tx.v new file mode 100644 index 0000000..a6afa00 --- /dev/null +++ b/rtl/ethernet-udp/src/eth/mac/tx/udp_tx.v @@ -0,0 +1,631 @@ +////////////////////////////////////////////////////////////////////////////////////// +//Module Name : udp_tx +//Description : This module is used to send UDP data and generate UDP checksum +// +////////////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ns +module udp_tx + ( + input clk, + input rst_n, + + input [31:0] source_ip_addr, + input [31:0] destination_ip_addr, + + input [15:0] udp_send_source_port, + input [15:0] udp_send_destination_port, + input [15:0] udp_send_data_length, + + input [7:0] ram_wr_data, //write data to udp tx ram + input ram_wr_en, //write en + output reg udp_ram_data_req, //request data written to ram + input mac_send_end, //mac send finished + input udp_tx_req, + output reg ip_tx_req, //udp reqest ip + input ip_tx_ack, //ip ack for udp transfer + input udp_data_req, + output reg udp_tx_ready, + output reg [7:0] udp_tx_data, + output reg udp_tx_end, + output almost_full + + ) ; + + +reg ram_rd_en ; +wire [3:0] usedw ; +reg [3:0] fifo_count ; + +reg [7:0] ram_rdata_d0 ; +reg [7:0] ram_rdata_d1 ; +reg [7:0] ram_wr_data_d0 ; +reg [7:0] ram_wr_data_d1 ; + +wire [7:0] ram_rdata ; +reg [5:0] ram_data_length ; + +reg [15:0] udp_send_cnt ; +reg [15:0] udp_data_length ; //valid data length +reg [15:0] udp_total_data_length ;//data length when transfer + +reg [15:0] timeout ; + +reg mac_send_end_d0 ; + + + +parameter IDLE = 6'b000001 ; +parameter START = 6'b000010 ; +parameter LEN_LATCH = 6'b000100 ; +parameter SEND_WAIT = 6'b001000 ; +parameter UDP_SEND = 6'b010000 ; +parameter UDP_END = 6'b100000 ; + + +reg [5:0] state ; +reg [5:0] next_state ; + + + reg [16:0] checksum_tmp0 ; + reg [16:0] checksum_tmp1 ; + reg [16:0] checksum_tmp2 ; + reg [16:0] checksum_tmp3 ; + reg [16:0] checksum_tmp4 ; + reg [17:0] checksum_tmp5 ; + reg [17:0] checksum_tmp6 ; + reg [18:0] checksum_tmp7 ; + reg [19:0] checksum_tmp8 ; + + reg [31:0] checksum_tmp9 ; + + reg [31:0] checksum_buf ; + reg [31:0] check_out ; + reg [31:0] checkout_buf ; + wire [15:0] checksum ; + reg [15:0] checksum_cnt ; + + reg checksum_wr ; + reg checksum_rd ; + reg [31:0] checksum_in ; + reg checksum_finish ; + reg [15:0] checksum_udp_len ; + wire [31:0] checksum_q ; + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + state <= IDLE ; + else + state <= next_state ; + end + +always @(*) + begin + case(state) + IDLE : + begin + if (usedw > 4'd0) + next_state <= START ; + else + next_state <= IDLE ; + end + START : + begin + next_state <= LEN_LATCH ; + end + LEN_LATCH : + begin + if (ip_tx_ack) + next_state <= SEND_WAIT ; + else + next_state <= LEN_LATCH ; + end + SEND_WAIT : + begin + if (udp_data_req) + next_state <= UDP_SEND ; + else if (timeout == 16'hffff) + next_state <= IDLE ; + else + next_state <= SEND_WAIT ; + end + + UDP_SEND : + begin + if (udp_send_cnt == udp_total_data_length) + next_state <= UDP_END ; + else + next_state <= UDP_SEND ; + end + UDP_END : + begin + if (mac_send_end_d0) + next_state <= IDLE ; + else + next_state <= UDP_END ; + end + default : + next_state <= IDLE ; + endcase + end + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + fifo_count <= 4'd0 ; + else + fifo_count <= usedw ; + end +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + checksum_rd <= 1'b0 ; + else if (state == IDLE && state != next_state) + checksum_rd <= 1'b1 ; + else + checksum_rd <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + ip_tx_req <= 1'b0 ; + else if (state == LEN_LATCH) + ip_tx_req <= 1'b1 ; + else + ip_tx_req <= 1'b0 ; + end + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + mac_send_end_d0 <= 1'b0 ; + else + mac_send_end_d0 <= mac_send_end ; + end + + +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + udp_tx_ready <= 1'b0 ; + else if (state == SEND_WAIT) + udp_tx_ready <= 1'b1 ; + else + udp_tx_ready <= 1'b0 ; + end + + + + +//timeout counter +always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + timeout <= 16'd0 ; + else if (state == SEND_WAIT) + timeout <= timeout + 1'b1 ; + else + timeout <= 16'd0 ; + end + +udp_tx_data_fifo tx_data_fifo + ( + .clk (clk ), // input wire clk + .srst (~rst_n ), // input wire srst + .din (ram_wr_data ), // input wire [7 : 0] din + .wr_en (ram_wr_en ), // input wire wr_en + .rd_en (ram_rd_en ), // input wire rd_en + .dout (ram_rdata ), // output wire [7 : 0] dout + .full ( ), // output wire full + .almost_full (almost_full ), // output wire almost_full + .empty ( ), // output wire empty + .data_count ( ) // output wire [11 : 0] data_count + ); + + + always @(posedge clk or negedge rst_n) + begin + if(rst_n == 1'b0) + begin + ram_wr_data_d0 <= 8'd0 ; + ram_wr_data_d1 <= 8'd0 ; + end + else + begin + ram_wr_data_d0 <= ram_wr_data ; + ram_wr_data_d1 <= ram_wr_data_d0 ; + end + end + //ram signal + + always @(posedge clk or negedge rst_n) + begin + if(rst_n == 1'b0) + begin + ram_rdata_d0 <= 8'd0 ; + ram_rdata_d1 <= 8'd0 ; + end + else + begin + ram_rdata_d0 <= ram_rdata ; + ram_rdata_d1 <= ram_rdata_d0 ; + end + end + + + + always @(posedge clk or negedge rst_n) + begin + if(rst_n == 1'b0) + ram_rd_en <= 1'b0 ; + else if (state == UDP_SEND && udp_send_cnt > 4 && udp_send_cnt < udp_data_length - 3) + ram_rd_en <= 1'b1 ; + else + ram_rd_en <= 1'b0 ; + end + + + //checksum counter + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + udp_send_cnt <= 16'd0 ; + else if (state == UDP_SEND) + udp_send_cnt <= udp_send_cnt + 1'b1 ; + else + udp_send_cnt <= 16'd0 ; + end + + + + reg [15:0] fifo_udp_len ; + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + fifo_udp_len <= 16'd0 ; + else + fifo_udp_len <= checksum_q[31:16] ; + end + //generate udp and ip data length + always @(posedge clk or negedge rst_n) + begin + if(rst_n == 1'b0) + begin + udp_total_data_length <= 16'd0 ; + udp_data_length <= 16'd0 ; + end + else if (state == LEN_LATCH) + begin + udp_data_length <= fifo_udp_len ; + if (fifo_udp_len < 26) + udp_total_data_length <= 26 ; + else + udp_total_data_length <= fifo_udp_len ; + end + end + + + + //*****************************************************************************************// + //send udp data + //*****************************************************************************************// + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + udp_tx_data <= 8'h00 ; + else if (state == UDP_SEND) + begin + case(udp_send_cnt) + 16'd0 : udp_tx_data <= udp_send_source_port[15:8] ; + 16'd1 : udp_tx_data <= udp_send_source_port[7:0] ; + 16'd2 : udp_tx_data <= udp_send_destination_port[15:8] ; + 16'd3 : udp_tx_data <= udp_send_destination_port[7:0] ; + 16'd4 : udp_tx_data <= udp_data_length[15:8] ; + 16'd5 : udp_tx_data <= udp_data_length[7:0] ; + 16'd6 : udp_tx_data <= checksum_q[15:8] ; + 16'd7 : udp_tx_data <= checksum_q[7:0] ; + default : + begin + if (udp_data_length < 26) + begin + if (udp_send_cnt <= udp_data_length - 1) + udp_tx_data <= ram_rdata_d0 ; + else + udp_tx_data <= 8'h00 ; + end + else + udp_tx_data <= ram_rdata_d0 ; + end + endcase + end + else + udp_tx_data <= 8'h00 ; + end + + + //*****************************************************************************************// + //generate udp checksum + //*****************************************************************************************// + localparam CK_IDLE = 6'b000001 ; + localparam HEADER_CHECKSUM = 6'b000010 ; + localparam GEN_CHECKSUM = 6'b000100 ; + localparam GEN_ODD_CHECKSUM = 6'b001000 ; + localparam GEN_CHECKSUM_END = 6'b010000 ; + localparam CHECKSUM_WAIT = 6'b100000 ; + + reg [5:0] ck_state ; + reg [5:0] ck_next_state ; + + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + ck_state <= IDLE ; + else + ck_state <= ck_next_state ; + end + + always @(*) + begin + case(ck_state) + CK_IDLE : + begin + if (udp_tx_req) + ck_next_state <= HEADER_CHECKSUM ; + else + ck_next_state <= CK_IDLE ; + end + HEADER_CHECKSUM : + begin + if (checksum_cnt == 16'd8) + begin + if (checksum_udp_len == 16'd9) + ck_next_state <= GEN_ODD_CHECKSUM ; + else + ck_next_state <= GEN_CHECKSUM ; + end + else + ck_next_state <= HEADER_CHECKSUM ; + end + GEN_CHECKSUM : + begin + if (checksum_udp_len[0] == 1'b0 && checksum_cnt == checksum_udp_len - 9) + ck_next_state <= GEN_CHECKSUM_END ; + else if (checksum_udp_len[0] == 1'b1 && checksum_cnt == checksum_udp_len - 10) + ck_next_state <= GEN_ODD_CHECKSUM ; + else + ck_next_state <= GEN_CHECKSUM ; + end + GEN_ODD_CHECKSUM: + begin + if (checksum_cnt == checksum_udp_len - 9) + ck_next_state <= GEN_CHECKSUM_END ; + else + ck_next_state <= GEN_ODD_CHECKSUM ; + end + GEN_CHECKSUM_END : + begin + if (checksum_finish) + ck_next_state <= CHECKSUM_WAIT ; + else + ck_next_state <= GEN_CHECKSUM_END ; + end + CHECKSUM_WAIT : + begin + ck_next_state <= CK_IDLE ; + end + default : + ck_next_state <= CK_IDLE ; + endcase + end + + + + //checksum function + function [31:0] checksum_adder + ( + input [31:0] dataina, + input [31:0] datainb + ); + + begin + checksum_adder = dataina + datainb; + end + endfunction + + function [31:0] checksum_out + ( + input [31:0] dataina + ); + + begin + checksum_out = dataina[15:0]+dataina[31:16]; + end + + endfunction + + + + always @(posedge clk or negedge rst_n) + begin + if(rst_n == 1'b0) + begin + checksum_tmp0 <= 17'd0 ; + checksum_tmp1 <= 17'd0 ; + checksum_tmp2 <= 17'd0 ; + checksum_tmp3 <= 17'd0 ; + checksum_tmp4 <= 17'd0 ; + checksum_tmp5 <= 18'd0 ; + checksum_tmp6 <= 18'd0 ; + checksum_tmp7 <= 19'd0 ; + checksum_tmp8 <= 20'd0 ; + end + else if (ck_state == HEADER_CHECKSUM) + begin + checksum_tmp0 <= checksum_adder(source_ip_addr[31:16],source_ip_addr[15:0]); //source ip address + checksum_tmp1 <= checksum_adder(destination_ip_addr[31:16],destination_ip_addr[15:0]); //destination ip address + checksum_tmp2 <= checksum_adder({8'd0,8'd17},checksum_udp_len); //protocol type + checksum_tmp3 <= checksum_adder(udp_send_source_port,udp_send_destination_port); //udp data length + checksum_tmp4 <= checksum_adder(checksum_udp_len, 16'd0); + checksum_tmp5 <= checksum_adder(checksum_tmp0, checksum_tmp1); + checksum_tmp6 <= checksum_adder(checksum_tmp2, checksum_tmp3); + checksum_tmp7 <= checksum_adder(checksum_tmp5, checksum_tmp6); + checksum_tmp8 <= checksum_adder(checksum_tmp4, checksum_tmp7); + end + else if (ck_state == CK_IDLE) + begin + checksum_tmp0 <= 17'd0 ; + checksum_tmp1 <= 17'd0 ; + checksum_tmp2 <= 17'd0 ; + checksum_tmp3 <= 17'd0 ; + checksum_tmp4 <= 17'd0 ; + checksum_tmp5 <= 18'd0 ; + checksum_tmp6 <= 18'd0 ; + checksum_tmp7 <= 19'd0 ; + checksum_tmp8 <= 20'd0 ; + end + + end + + always @(posedge clk or negedge rst_n) + begin + if(rst_n == 1'b0) + checksum_tmp9 <= 32'd0 ; + else if (ck_state == GEN_CHECKSUM) + begin + if(checksum_cnt[0] == 1'b1) + checksum_tmp9 <= checksum_adder({ram_wr_data_d1,ram_wr_data_d0},checksum_buf); + end + else if (ck_state == GEN_ODD_CHECKSUM) + checksum_tmp9 <= checksum_adder({ram_wr_data_d0,8'h00},checksum_tmp9); //if udp data length is odd, fill with one byte 8'h00 + else if (ck_state == CK_IDLE) + checksum_tmp9 <= 32'd0 ; + end + + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + checksum_buf <= 32'd0 ; + else if (ck_state == GEN_CHECKSUM) + checksum_buf <= checksum_tmp9 ; + else + checksum_buf <= 32'd0 ; + end + + always @(posedge clk or negedge rst_n) + begin + if(rst_n == 1'b0) + checksum_cnt <= 16'd0 ; + else if ((ck_state == HEADER_CHECKSUM || ck_state == GEN_ODD_CHECKSUM || ck_state == GEN_CHECKSUM_END) && (ck_state != ck_next_state)) + checksum_cnt <= 16'd0 ; + else if (ck_state == GEN_CHECKSUM && ck_next_state == GEN_CHECKSUM_END) + checksum_cnt <= 16'd0 ; + else if (ck_state == HEADER_CHECKSUM || ck_state == GEN_CHECKSUM || ck_state == GEN_ODD_CHECKSUM || ck_state == GEN_CHECKSUM_END) + checksum_cnt <= checksum_cnt + 1'b1 ; + else + checksum_cnt <= 16'd0 ; + end + + always @(posedge clk or negedge rst_n) + begin + if(rst_n == 1'b0) + check_out <= 32'd0; + else if (ck_state == GEN_CHECKSUM_END) + begin + if(checksum_cnt == 16'd0) + check_out <= checksum_adder(checksum_tmp9, checksum_tmp8); + else if (checksum_cnt == 16'd1) + check_out <= checksum_out(check_out) ; + else if (checksum_cnt == 16'd2) + check_out <= checksum_out(check_out) ; + end + end + + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + checkout_buf <= 32'd0 ; + else if (ck_state == GEN_CHECKSUM_END) + checkout_buf <= ~check_out ; + end + + // assign checksum = ~checkout_buf[15:0] ; + + + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + checksum_finish <= 1'b0 ; + else if (ck_state == GEN_CHECKSUM_END && checksum_cnt == 16'd4) + checksum_finish <= 1'b1 ; + else + checksum_finish <= 1'b0 ; + end + + + always @(posedge clk or negedge rst_n) + begin + if(rst_n == 1'b0) + udp_ram_data_req <= 1'b0 ; + else if (ck_state == HEADER_CHECKSUM && checksum_cnt == 16'd5) + udp_ram_data_req <= 1'b1 ; + else + udp_ram_data_req <= 1'b0 ; + end + + + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + checksum_wr <= 1'b0 ; + else if (ck_state == CHECKSUM_WAIT) + checksum_wr <= 1'b1 ; + else + checksum_wr <= 1'b0 ; + end + + + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + checksum_udp_len <= 16'd0 ; + else if ((ck_state == CK_IDLE) && (ck_state != ck_next_state)) + checksum_udp_len <= udp_send_data_length + 8 ; + end + + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + checksum_in <= 32'd0 ; + else if (ck_state == CHECKSUM_WAIT) + checksum_in <= {checksum_udp_len, checkout_buf[15:0] } ; + else + checksum_in <= 32'd0 ; + end + + always @(posedge clk or negedge rst_n) + begin + if (~rst_n) + udp_tx_end <= 1'b0 ; + else if (ck_state == CHECKSUM_WAIT) + udp_tx_end <= 1'b1 ; + else + udp_tx_end <= 1'b0 ; + end + +udp_checksum_fifo udp_tx_checksum +( + .clk (clk ), // input wire clk + .srst (~rst_n ), // input wire srst + .din (checksum_in), // input wire [31 : 0] din + .wr_en (checksum_wr), // input wire wr_en + .rd_en (checksum_rd), // input wire rd_en + .dout (checksum_q ), // output wire [31 : 0] dout + .full ( ), // output wire full + .empty ( ), // output wire empty + .data_count (usedw ) // output wire [3 : 0] data_count +); + +endmodule diff --git a/rtl/ethernet-udp/src/eth/reset.v b/rtl/ethernet-udp/src/eth/reset.v new file mode 100644 index 0000000..f462f57 --- /dev/null +++ b/rtl/ethernet-udp/src/eth/reset.v @@ -0,0 +1,20 @@ + +module reset( + input clk, + input key1, + output rst_n +); +reg[27:0] cnt = 28'd0; +reg rst_n_reg; +assign rst_n = rst_n_reg; +always@(posedge clk) + if(key1==1'b0) + cnt <= 0; + else + if(cnt != 28'h3ffffff) + cnt <= cnt + 1'd1; + else + cnt <= cnt; +always@(posedge clk) + rst_n_reg <= (cnt == 28'h3ffffff); +endmodule diff --git a/rtl/ethernet-udp/src/eth/util_gmii_to_rgmii.v b/rtl/ethernet-udp/src/eth/util_gmii_to_rgmii.v new file mode 100644 index 0000000..4f457d7 --- /dev/null +++ b/rtl/ethernet-udp/src/eth/util_gmii_to_rgmii.v @@ -0,0 +1,253 @@ +module util_gmii_to_rgmii ( + reset, + sys_clk, + rgmii_td, + rgmii_tx_ctl, + rgmii_txc, + rgmii_rd, + rgmii_rx_ctl, + gmii_rx_clk, + rgmii_rxc, + gmii_txd, + gmii_tx_en, + gmii_tx_er, + gmii_tx_clk, + gmii_crs, + gmii_col, + gmii_rxd, + gmii_rx_dv, + gmii_rx_er, + speed_selection, + duplex_mode, + rgmii_rx_ctl_idelay + ); + input rgmii_rxc;//add + input reset; + input sys_clk; + output [ 3:0] rgmii_td; + output rgmii_tx_ctl; + output rgmii_txc; + input [ 3:0] rgmii_rd; + input rgmii_rx_ctl; + output gmii_rx_clk; + input [ 7:0] gmii_txd; + input gmii_tx_en; + input gmii_tx_er; + output gmii_tx_clk; + output gmii_crs; + output gmii_col; + output [ 7:0] gmii_rxd; + output gmii_rx_dv; + output gmii_rx_er; + input [ 1:0] speed_selection; // 1x gigabit, 01 100Mbps, 00 10mbps + input duplex_mode; // 1 full, 0 half + output rgmii_rx_ctl_idelay; + + + wire gigabit; + wire gmii_tx_clk_s; + wire gmii_rx_dv_s; + + wire [ 7:0] gmii_rxd_s; + wire rgmii_rx_ctl_delay; + wire rgmii_rx_ctl_s; + // registers + reg tx_reset_d1; + reg tx_reset_sync; + reg rx_reset_d1; + reg [ 7:0] gmii_txd_r; + reg gmii_tx_en_r; + reg gmii_tx_er_r; + reg [ 7:0] gmii_txd_r_d1; + reg gmii_tx_en_r_d1; + reg gmii_tx_er_r_d1; + + reg rgmii_tx_ctl_r; + reg [ 3:0] gmii_txd_low; + reg gmii_col; + reg gmii_crs; + + reg [ 7:0] gmii_rxd; + reg gmii_rx_dv; + reg gmii_rx_er; + wire gmii_rx_clk_s; + reg[1:0] speed_selection_d0; + reg[1:0] speed_selection_d1; + + wire [3:0] rgmii_rd_idelay; + wire [4:0] cntvaluein ; + wire [4:0] cntvalueout ; + wire ld ; + always @(posedge gmii_rx_clk) + begin + speed_selection_d0<= speed_selection; + speed_selection_d1<= speed_selection_d0; + end + //assign gigabit = speed_selection [1]; + assign gigabit = 1'b1; + assign gmii_tx_clk = gmii_tx_clk_s; + assign gmii_tx_clk_s = gmii_rx_clk; +// assign gmii_rx_clk =~gmii_rx_clk_s; +// assign gmii_rx_clk=speed_selection_d0[1]?gmii_rx_clk_s:gmii_rx_clk_s; +// BUFG bufmr_rgmii_rxc( +// .I(rgmii_rxc), +// .O(gmii_rx_clk) +// ); + assign gmii_rx_clk=rgmii_rxc; + always @(posedge gmii_rx_clk) + begin + gmii_rxd = gmii_rxd_s; + gmii_rx_dv = gmii_rx_dv_s; + gmii_rx_er = gmii_rx_dv_s ^ rgmii_rx_ctl_s; + end + + always @(posedge gmii_tx_clk_s) begin + tx_reset_d1 <= reset; + tx_reset_sync <= tx_reset_d1; + end + + always @(posedge gmii_tx_clk_s) + begin + rgmii_tx_ctl_r = gmii_tx_en_r ^ gmii_tx_er_r; + gmii_txd_low = gigabit ? gmii_txd_r[7:4] : gmii_txd_r[3:0]; + gmii_col = duplex_mode ? 1'b0 : (gmii_tx_en_r| gmii_tx_er_r) & ( gmii_rx_dv | gmii_rx_er) ; + gmii_crs = duplex_mode ? 1'b0 : (gmii_tx_en_r| gmii_tx_er_r| gmii_rx_dv | gmii_rx_er); + end + + always @(posedge gmii_tx_clk_s) begin + if (tx_reset_sync == 1'b1) begin + gmii_txd_r <= 8'h0; + gmii_tx_en_r <= 1'b0; + gmii_tx_er_r <= 1'b0; + end + else + begin + gmii_txd_r <= gmii_txd; + gmii_tx_en_r <= gmii_tx_en; + gmii_tx_er_r <= gmii_tx_er; + gmii_txd_r_d1 <= gmii_txd_r; + gmii_tx_en_r_d1 <= gmii_tx_en_r; + gmii_tx_er_r_d1 <= gmii_tx_er_r; + end + end + + + ODDR #( + .DDR_CLK_EDGE("SAME_EDGE") + ) rgmii_txc_out ( + .Q (rgmii_txc), + .C (gmii_tx_clk_s), + .CE(1), + .D1(1), + .D2(0), + .R(tx_reset_sync), + .S(0)); + + generate + genvar i; + for (i = 0; i < 4; i = i + 1) begin : gen_tx_data + ODDR #( + .DDR_CLK_EDGE("SAME_EDGE") + ) rgmii_td_out ( + .Q (rgmii_td[i]), + .C (gmii_tx_clk_s), + .CE(1), + .D1(gmii_txd_r_d1[i]), + .D2(gmii_txd_low[i]), + .R(tx_reset_sync), + .S(0)); + end + endgenerate + + ODDR #( + .DDR_CLK_EDGE("SAME_EDGE") + ) rgmii_tx_ctl_out ( + .Q (rgmii_tx_ctl), + .C (gmii_tx_clk_s), + .CE(1), + .D1(gmii_tx_en_r_d1), + .D2(rgmii_tx_ctl_r), + .R(tx_reset_sync), + .S(0)); + + generate + for (i = 0; i < 4; i = i + 1) begin + + (* IODELAY_GROUP = "rgmii_idelay_group" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL + + IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE) + .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN) + .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE") + .IDELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE + .IDELAY_VALUE(16), // Input delay tap setting (0-31) + .PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE + .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0). + .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal + ) + IDELAYE2_inst ( + .CNTVALUEOUT(), // 5-bit output: Counter value output + .DATAOUT(rgmii_rd_idelay[i]), // 1-bit output: Delayed data output + .C(gmii_rx_clk), // 1-bit input: Clock input + .CE(0), // 1-bit input: Active high enable increment/decrement input + .CINVCTRL(0), // 1-bit input: Dynamic clock inversion input + .CNTVALUEIN(0), // 5-bit input: Counter value input + .DATAIN(0), // 1-bit input: Internal delay data input + .IDATAIN(rgmii_rd[i]), // 1-bit input: Data input from the I/O + .INC(0), // 1-bit input: Increment / Decrement tap delay input + .LD(0), // 1-bit input: Load IDELAY_VALUE input + .LDPIPEEN(0), // 1-bit input: Enable PIPELINE register to load data input + .REGRST(0) // 1-bit input: Active-high reset tap-delay input + ); + + IDDR #( + .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + ) rgmii_rx_iddr ( + .Q1(gmii_rxd_s[i]), + .Q2(gmii_rxd_s[i+4]), + .C(gmii_rx_clk), + .CE(1), + .D(rgmii_rd_idelay[i]), + .R(0), + .S(0)); + end + endgenerate + + (* IODELAY_GROUP = "rgmii_idelay_group" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL + IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE) + .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN) + .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE") + .IDELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE + .IDELAY_VALUE(16), // Input delay tap setting (0-31) + .PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE + .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0). + .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal + ) + IDELAYE2_ctrl_inst ( + .CNTVALUEOUT(), // 5-bit output: Counter value output + .DATAOUT(rgmii_rx_ctl_idelay), // 1-bit output: Delayed data output + .C(gmii_rx_clk), // 1-bit input: Clock input + .CE(0), // 1-bit input: Active high enable increment/decrement input + .CINVCTRL(0), // 1-bit input: Dynamic clock inversion input + .CNTVALUEIN(0), // 5-bit input: Counter value input + .DATAIN(0), // 1-bit input: Internal delay data input + .IDATAIN(rgmii_rx_ctl), // 1-bit input: Data input from the I/O + .INC(0), // 1-bit input: Increment / Decrement tap delay input + .LD(0), // 1-bit input: Load IDELAY_VALUE input + .LDPIPEEN(0), // 1-bit input: Enable PIPELINE register to load data input + .REGRST(0) // 1-bit input: Active-high reset tap-delay input + ); + + IDDR #( + .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + ) rgmii_rx_ctl_iddr ( + .Q1(gmii_rx_dv_s), + .Q2(rgmii_rx_ctl_s), + .C(gmii_rx_clk), + .CE(1), + .D(rgmii_rx_ctl_idelay), + .R(0), + .S(0)); + +endmodule diff --git a/rtl/ethernet-udp/src/ip/eth_data_fifo/eth_data_fifo.xci b/rtl/ethernet-udp/src/ip/eth_data_fifo/eth_data_fifo.xci new file mode 100644 index 0000000..c823031 --- /dev/null +++ b/rtl/ethernet-udp/src/ip/eth_data_fifo/eth_data_fifo.xci @@ -0,0 +1,461 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": 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[ { "physical_name": "addrb" } ], + "CLK": [ { "physical_name": "clkb" } ], + "DOUT": [ { "physical_name": "doutb" } ] + } + } + }, + "memory_maps": { + "S_1": { + "address_blocks": { + "Mem0": { + "base_address": "0", + "range": "4096", + "usage": "memory", + "access": "read-write", + "parameters": { + "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ], + "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ] + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/rtl/ethernet-udp/src/ip/len_fifo/len_fifo.xci b/rtl/ethernet-udp/src/ip/len_fifo/len_fifo.xci new file mode 100644 index 0000000..9352835 --- /dev/null +++ b/rtl/ethernet-udp/src/ip/len_fifo/len_fifo.xci @@ -0,0 +1,461 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "len_fifo", + "component_reference": "xilinx.com:ip:fifo_generator:13.2", + "ip_revision": "13", + "gen_directory": "../../../../ethernet_test.gen/sources_1/ip/len_fifo", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "len_fifo", "resolve_type": "user", "usage": "all" } ], + "Fifo_Implementation": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ], + "synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], + "synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], + "INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ], + "Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ], + "asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Input_Data_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Input_Depth": [ { "value": "32", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + 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