reflectometer with dma reformed

designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv

@@ -0,0 +1,178 @@
+module reflectometer_and_dma_wrapper 
+#(
+    // parameters for base reflectometer works
+    parameter int unsigned DAC_DATA_WIDTH = 14,
+    parameter int unsigned ADC_DATA_WIDTH = 12,
+    parameter int unsigned PACK_FACTOR = 1,
+    parameter int unsigned PROCESS_MODE = 0,
+    parameter int unsigned ZERO_LEVEL = 8192,
+    parameter int unsigned ACCUM_WIDTH = 32,
+    parameter int unsigned N_MAX = 4096,
+    parameter int unsigned PACKET_SIZE = 1024,
+    parameter int unsigned RD_FIFO_WIDTH = 32,
+
+    // parameters for DMA and interfaces
+    parameter int unsigned ADDR_W             = 16,
+    parameter int unsigned DATA_W             = 32,
+    parameter int unsigned USER_W             = 1,
+
+    parameter int unsigned DAC_DATA_WIDTH     = 12,
+
+    parameter int unsigned AXI_DATA_WIDTH     = 32,
+
+    parameter int unsigned AXI_STRB_WIDTH     = AXI_DATA_WIDTH / 8,
+    parameter int unsigned AXI_ID_WIDTH       = 8,
+    parameter int unsigned AXI_USER_WIDTH     = 1,
+    parameter int unsigned AXI_MAX_BURST_LEN  = 16,
+
+    parameter int unsigned AXIS_DATA_WIDTH    = AXI_DATA_WIDTH,
+    parameter int unsigned AXIS_KEEP_ENABLE   = AXIS_DATA_WIDTH > 8,
+    parameter int unsigned AXIS_KEEP_WIDTH    = AXIS_DATA_WIDTH / 8,
+    parameter int unsigned AXIS_LAST_ENABLE   = 1,
+    parameter int unsigned AXIS_ID_ENABLE     = 1,
+    parameter int unsigned AXIS_DEST_ENABLE   = 0,
+    parameter int unsigned AXIS_USER_ENABLE   = 1,
+
+    parameter int unsigned ENABLE_SG          = 0,
+    parameter int unsigned ENABLE_UNALIGNED   = 0,
+
+    parameter int unsigned PIPELINE_OUTPUT    = 0
+)
+(
+    input  logic                       ctrl_clk,
+    input  logic                       rst_n,
+    output  wire                       locked,
+
+    axi4l_if.slave                     s_axil,
+    axi4_if.master                     m_axi,
+    axi4s_if.master                    m_axis_read_data,
+
+        // DAC
+    output  wire                        dac_clk_o,
+    output  wire [DAC_DATA_WIDTH-1:0]   dac_data,
+    output  wire                        dac_wrt,
+
+    // ADC
+    output  wire                        adc_clk_o,
+    input   wire [ADC_DATA_WIDTH-1:0]   adc_data,
+    input   wire                        adc_otr
+
+
+);
+
+    axis_if #(
+    .DATA_W($bits(dma_read_status_t)),
+    .KEEP_W(($bits(dma_read_status_t)+7)/8),
+    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
+    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
+    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
+  ) s_axis_status_read (
+    .aclk(ctrl_clk),
+    .aresetn(rst_n)
+  );
+
+  axis_if #(
+    .DATA_W($bits(dma_write_status_t)),
+    .KEEP_W(($bits(dma_write_status_t)+7)/8),
+    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
+    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
+    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
+  ) s_axis_status_write (
+    .aclk(ctrl_clk),
+    .aresetn(rst_n)
+  );
+
+  axis_if #(
+    .DATA_W($bits(dma_read_desc_t)),
+    .KEEP_W(($bits(dma_read_desc_t)+7)/8),
+    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
+    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
+    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
+  ) m_axis_desc_read (
+    .aclk(ctrl_clk),
+    .aresetn(rst_n)
+  );
+
+  axis_if #(
+    .DATA_W($bits(dma_write_desc_t)),
+    .KEEP_W(($bits(dma_write_desc_t)+7)/8),
+    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
+    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
+    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
+  ) m_axis_desc_write (
+    .aclk(ctrl_clk),
+    .aresetn(rst_n)
+  );
+
+  axis_if #(
+    .DATA_W(RD_FIFO_WIDTH),
+    .KEEP_W((RD_FIFO_WIDTH+7)/8),
+    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
+    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
+    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
+  ) m_axis_accum (
+    .aclk(ctrl_clk),
+    .aresetn(rst_n)
+  );
+
+    reflectometer_top #(
+        .DAC_DATA_WIDTH(DAC_DATA_WIDTH),
+        .ADC_DATA_WIDTH(ADC_DATA_WIDTH),
+        .ADC_DATA_WIDTH(ADC_DATA_WIDTH),
+        .PACK_FACTOR(PACK_FACTOR),
+        .PROCESS_MODE(PROCESS_MODE),
+        .ZERO_LEVEL(ZERO_LEVEL),
+        .ACCUM_WIDTH(ACCUM_WIDTH),
+        .N_MAX(N_MAX),
+        .PACKET_SIZE(PACKET_SIZE),
+        .RD_FIFO_WIDTH(RD_FIFO_WIDTH)
+    ) reflectometer_top_inst (
+        .ctrl_clk(ctrl_clk),
+        .rst_n(rst_n),
+        .locked(locked),
+        .s_axil(s_axil),
+        .m_axis_accum(m_axis_accum),
+        .s_axis_status_read(s_axis_status_read),
+        .s_axis_status_write(s_axis_status_write),
+        .m_axis_desc_read(m_axis_desc_read),
+        .m_axis_desc_write(m_axis_desc_write),
+
+        .dac_clk_o(dac_clk_o),
+        .dac_data(dac_data),
+        .dac_wrt(dac_wrt),
+        .adc_clk_o(adc_clk_o),
+        .adc_data(adc_data),
+        .adc_otr(adc_otr)
+    );
+
+    //------------------------------------------------------------
+    // DMA
+    //------------------------------------------------------------
+    axi_dma_wrapper #(
+        .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
+        .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
+        .AXI_USER_WIDTH(AXI_USER_WIDTH),
+        .AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
+        .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
+        .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
+        .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
+        .AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
+        .AXIS_ID_ENABLE(AXIS_ID_ENABLE),
+        .AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
+        .AXIS_USER_ENABLE(AXIS_USER_ENABLE),
+        .ENABLE_SG(ENABLE_SG),
+        .ENABLE_UNALIGNED(ENABLE_UNALIGNED)
+    ) axi_dma_wrapper_inst
+    (
+        .clk(ctrl_clk),
+        .rst(!ctrl_rst_n),
+        .s_axis_read_desc(m_axis_desc_read),
+        .m_axis_read_desc_status(s_axis_status_read),
+        .m_axis_read_data(m_axis_read_data),
+        .s_axis_write_desc(m_axis_desc_write),
+        .m_axis_write_desc_status(s_axis_status_write),
+        .s_axis_write_data(m_axis_accum),
+        .m_axi(m_axi)
+    );
+
+endmodule

designs/full_new_reflectometer/src/reflectometer_ip.sv

@@ -15,29 +15,7 @@ module reflectometer_top #(
         // parameters for DMA and interfaces
     parameter int unsigned ADDR_W             = 16,
     parameter int unsigned DATA_W             = 32,
-    parameter int unsigned USER_W             = 1,
+    parameter int unsigned USER_W             = 1
-
-    parameter int unsigned DAC_DATA_WIDTH     = 12,
-
-    parameter int unsigned AXI_DATA_WIDTH     = 32,
-
-    parameter int unsigned AXI_STRB_WIDTH     = AXI_DATA_WIDTH / 8,
-    parameter int unsigned AXI_ID_WIDTH       = 8,
-    parameter int unsigned AXI_USER_WIDTH     = 1,
-    parameter int unsigned AXI_MAX_BURST_LEN  = 16,
-
-    parameter int unsigned AXIS_DATA_WIDTH    = AXI_DATA_WIDTH,
-    parameter int unsigned AXIS_KEEP_ENABLE   = AXIS_DATA_WIDTH > 8,
-    parameter int unsigned AXIS_KEEP_WIDTH    = AXIS_DATA_WIDTH / 8,
-    parameter int unsigned AXIS_LAST_ENABLE   = 1,
-    parameter int unsigned AXIS_ID_ENABLE     = 1,
-    parameter int unsigned AXIS_DEST_ENABLE   = 0,
-    parameter int unsigned AXIS_USER_ENABLE   = 1,
-
-    parameter int unsigned ENABLE_SG          = 0,
-    parameter int unsigned ENABLE_UNALIGNED   = 0,
-
-    parameter int unsigned PIPELINE_OUTPUT    = 0
 )
 (
     input  logic                       ctrl_clk,
@@ -45,8 +23,11 @@ module reflectometer_top #(
     output  wire                       locked,
 
     axi4l_if.slave                     s_axil,
-    axi4_if.master                     m_axi,
+    axis_if.master                     m_axis_accum,
-    axi4s_if.master                    m_axis_read_data,
+    axis_if.slave                      s_axis_status_read,
+    axis_if.slave                      s_axis_status_write,
+    axis_if.master                     m_axis_desc_read,
+    axis_if.master                     m_axis_desc_write,
 
         // DAC
     output  wire                        dac_clk_o,
@@ -61,61 +42,6 @@ module reflectometer_top #(
 
 );
 
-axis_if #(
-    .DATA_W($bits(dma_read_status_t)),
-    .KEEP_W(($bits(dma_read_status_t)+7)/8),
-    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
-    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
-    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
-  ) s_axis_status_read (
-    .aclk(ctrl_clk),
-    .aresetn(rst_n)
-  );
-
-  axis_if #(
-    .DATA_W($bits(dma_write_status_t)),
-    .KEEP_W(($bits(dma_write_status_t)+7)/8),
-    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
-    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
-    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
-  ) s_axis_status_write (
-    .aclk(ctrl_clk),
-    .aresetn(rst_n)
-  );
-
-  axis_if #(
-    .DATA_W($bits(dma_read_desc_t)),
-    .KEEP_W(($bits(dma_read_desc_t)+7)/8),
-    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
-    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
-    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
-  ) m_axis_desc_read (
-    .aclk(ctrl_clk),
-    .aresetn(rst_n)
-  );
-
-  axis_if #(
-    .DATA_W($bits(dma_write_desc_t)),
-    .KEEP_W(($bits(dma_write_desc_t)+7)/8),
-    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
-    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
-    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
-  ) m_axis_desc_write (
-    .aclk(ctrl_clk),
-    .aresetn(rst_n)
-  );
-
-  axis_if #(
-    .DATA_W(RD_FIFO_WIDTH),
-    .KEEP_W((RD_FIFO_WIDTH+7)/8),
-    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
-    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
-    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
-  ) m_axis_accum (
-    .aclk(ctrl_clk),
-    .aresetn(rst_n)
-  );
-
 wire workflow_done, processing_done;
 
     // -------------------------------------------------------------------------
@@ -205,36 +131,6 @@ wire workflow_done, processing_done;
         .m_axis_desc_write(m_axis_desc_write)
     );
 
-    //------------------------------------------------------------
-    // DMA
-    //------------------------------------------------------------
-    axi_dma_wrapper #(
-        .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
-        .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
-        .AXI_USER_WIDTH(AXI_USER_WIDTH),
-        .AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
-        .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
-        .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
-        .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
-        .AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
-        .AXIS_ID_ENABLE(AXIS_ID_ENABLE),
-        .AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
-        .AXIS_USER_ENABLE(AXIS_USER_ENABLE),
-        .ENABLE_SG(ENABLE_SG),
-        .ENABLE_UNALIGNED(ENABLE_UNALIGNED)
-    ) axi_dma_wrapper_inst
-    (
-        .clk(ctrl_clk),
-        .rst(!ctrl_rst_n),
-        .s_axis_read_desc(m_axis_desc_read),
-        .m_axis_read_desc_status(s_axis_status_read),
-        .m_axis_read_data(m_axis_read_data),
-        .s_axis_write_desc(m_axis_desc_write),
-        .m_axis_write_desc_status(s_axis_status_write),
-        .s_axis_write_data(m_axis_accum),
-        .m_axi(m_axi)
-    );
-
     //------------------------------------------------------------
     // DAC -> ADC CDC
     //------------------------------------------------------------