makefile of the project

designs/full_new_reflectometer/tests/Makefile

@@ -0,0 +1,75 @@
+TOPLEVEL_LANG = verilog
+SIM ?= verilator
+
+PWD := $(shell pwd)
+
+WRAP_DIR = $(PWD)/../src
+RTL_CTRL_DIR  = $(PWD)/../../controller_new/src
+RTL_ACCUM_DIR = $(PWD)/../../accum/src
+RTL_GENERATOR_DIR = $(PWD)/../../generator/src
+RTL_SAMPLER_DIR = $(PWD)/../../sampler/src
+RTL_ADC_DAC_MODELS_DIR = $(PWD)/../reflectometer_base
+LIBS_DIR = $(PWD)/../../../external/rtl_libs
+
+#axi primitives
+VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_pkg.sv
+VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_if.sv
+VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axis_if.sv
+VERILOG_SOURCES += $(LIBS_DIR)/axi/axi_reg/axi4l_reg_map.sv
+
+#dma primitives
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/dma_reg_pkg.sv
+VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_rd.v
+VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_wr.v
+VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma.v
+VERILOG_SOURCES += $(WRAP_DIR)/axi_dma_wrapper_if.sv
+
+# controller primitives
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/controller.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/dma_controller.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/shaper_axis_desc.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/shaper_axis_status.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/controller_wrapper_axil.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/axi4l_reg_map_controller_pkg.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/axis_defaults_helper.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/axi4l_reg_map_controller.sv
+
+# accumulator primitives
+VERILOG_SOURCES += $(RTL_ACCUM_DIR)/adder.sv
+VERILOG_SOURCES += $(RTL_ACCUM_DIR)/accum.sv
+VERILOG_SOURCES += $(RTL_ACCUM_DIR)/out_axis_fifo.sv
+VERILOG_SOURCES += $(RTL_ACCUM_DIR)/accum_top.sv
+
+# generator primitives
+VERILOG_SOURCES += $(RTL_GENERATOR_DIR)/generator.sv
+
+#sampler_primitives
+VERILOG_SOURCES += $(RTL_SAMPLER_DIR)/sampler.sv
+
+# project primitives
+VERILOG_SOURCES += $(WRAP_DIR)/reflectometer_ip.sv
+VERILOG_SOURCES += $(WRAP_DIR)/reflectometer_and_dma_wrapper.sv
+
+# testbench primitives
+VERILOG_SOURCES += $(RTL_ADC_DAC_MODELS_DIR)/adc_model.sv
+VERILOG_SOURCES += $(RTL_ADC_DAC_MODELS_DIR)/dac_model.sv
+VERILOG_SOURCES += $(PWD)/tb_reflectometer_and_dma_wrapper.sv
+
+TOPLEVEL = tb_reflectometer_and_dma_wrapper
+MODULE = test_reflectometer_and_dma
+
+
+ifeq ($(SIM),verilator)
+    EXTRA_ARGS += --trace --trace-structs
+    EXTRA_ARGS += -I$(LIBS_DIR)/axi/rtl/
+    COMPILE_ARGS += -Wno-fatal
+    COMPILE_ARGS += -I$(LIBS_DIR)/axi/rtl/
+    EXTRA_ARGS += --trace
+    EXTRA_ARGS += --trace-structs
+    EXTRA_ARGS += --public-flat-rw
+    EXTRA_ARGS += -Wno-fatal
+    EXTRA_ARGS += --timing
+endif
+
+
+include $(shell cocotb-config --makefiles)/Makefile.sim