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fix: revert synchronizer changes (false changes) and sampler

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babintsev.lv
2026-07-14 13:02:55 +03:00
parent 493d6844c0
commit d80f5ff31f
7 changed files with 706 additions and 244 deletions
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49
designs/adc_dac_synchoronizer/sync_top.sv
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@ -6,7 +6,8 @@ module sync_top
parameter int unsigned ADC_DATA_WIDTH = 12, // ADC bit-width
parameter int unsigned PACK_FACTOR = 1, // number of ADC readings per transaction
parameter int unsigned PROCESS_MODE = 0, // representation format of ADC readings (0 - direct code, 1 - 2's completment)
parameter int unsigned ZERO_LEVEL = 0
parameter int unsigned ZERO_LEVEL = 0,
parameter int unsigned USE_DELAY_LINE = 0
)
(
input clk_adc,
@ -16,9 +17,9 @@ module sync_top
input start,
input out_of_range,
input [31:0] pulse_width,
input [31:0] pulse_period,
input [31:0] pulse_period, // DAC counter limit
input [DAC_DATA_WIDTH-1:0] pulse_height,
input [15:0] pulse_num, // DAC counter limit
input [15:0] pulse_num,
input [31:0] smp_num, // ADC counter limit
output [ADC_DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
output m_axis_tvalid
@ -29,13 +30,45 @@ module sync_top
//------------------------------------------------------------
wire dac_done, dac_request, adc_done, adc_request;
wire [DAC_DATA_WIDTH-1:0] dac_signal;
wire [ADC_DATA_WIDTH-1:0] adc_singnal;
wire [ADC_DATA_WIDTH-1:0] internal_wire_signal;
wire [ADC_DATA_WIDTH-1:0] adc_signal;
// 1. Адаптация разрядности и «заземление» лишних бит
generate
if (ADC_DATA_WIDTH > DAC_DATA_WIDTH) begin : g_pad_zeros
assign adc_singnal = { {(ADC_DATA_WIDTH - DAC_DATA_WIDTH){1'b0}}, dac_signal };
// АЦП шире ЦАП: добиваем нулями старшие биты
assign internal_wire_signal = { {(ADC_DATA_WIDTH - DAC_DATA_WIDTH){1'b0}}, dac_signal };
end
else if (ADC_DATA_WIDTH < DAC_DATA_WIDTH) begin : g_truncate
// ЦАП шире АЦП (например, 14 -> 12): забираем младшие биты
assign internal_wire_signal = dac_signal[DAC_DATA_WIDTH-1:DAC_DATA_WIDTH-ADC_DATA_WIDTH];
// (* mark_debug = "true" *) wire dummy;
// assign dummy = ^dac_signal;
end
else begin : g_match
// Разрядности равны
assign internal_wire_signal = dac_signal;
end
endgenerate
generate
if (USE_DELAY_LINE > 0) begin : g_delay_line
localparam int DELAY_LENGTH = USE_DELAY_LINE;
// Двумерный массив для линии задержки
logic [DELAY_LENGTH-1:0][ADC_DATA_WIDTH-1:0] signal_delay_line;
always_ff @(posedge clk_dac) begin
signal_delay_line[0] <= internal_wire_signal;
for (int i = 0; i < DELAY_LENGTH-1; i++) begin
signal_delay_line[i+1] <= signal_delay_line[i];
end
end
// ИСПРАВЛЕНО: читаем из последнего элемента массива
assign adc_signal = signal_delay_line[DELAY_LENGTH-1];
end
else begin : g_truncate
assign adc_singnal = dac_signal[ADC_DATA_WIDTH-1:0];
else begin : g_no_delay
assign adc_signal = internal_wire_signal;
end
endgenerate
@ -112,7 +145,7 @@ module sync_top
) sampler_inst (
.clk_in(clk_adc),
.rst(rst_adc),
.data_in(adc_singnal),
.data_in(adc_signal),
.out_of_range(out_of_range),
.smp_num(smp_num),
.m_axis_tdata(m_axis_tdata),