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fix: revert synchronizer changes (false changes) and sampler

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babintsev.lv
2026-07-14 13:02:55 +03:00
parent 493d6844c0
commit d80f5ff31f
7 changed files with 706 additions and 244 deletions
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13
designs/adc_dac_synchoronizer/debug.xdc
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@ -1,3 +1,12 @@
# Primary clocks
create_clock -name eth_clk -period 8.000 [get_ports clk_dac]
create_clock -name acc_clk -period 15.385 [get_ports clk_adc]
create_clock -name geneartor_clk -period 8.000 [get_ports clk_dac]
create_clock -name sampler_clk -period 15.385 [get_ports clk_adc]
set_clock_groups -asynchronous -group [get_clocks geneartor_clk] -group [get_clocks sampler_clk]
# set_false_path -through [get_nets -hierarchical {*dac_signal* *internal_wire_singnal* *adc_singnal*}]
# set_false_path -through [get_nets {dac_done dac_done_stretched dac_request adc_done adc_request}]
set_property DONT_TOUCH true [get_cells -hierarchical -filter {NAME =~ *generator_inst*pulse_height_reg*}]
set_property DONT_TOUCH true [get_cells -hierarchical -filter {NAME =~ *generator_inst*dac_out_reg*}]
# Применяем к самому проводу сигнала CE, чтобы Vivado не дробила его
# set_property DONT_TOUCH true [get_nets -of_objects [get_pins -hierarchical -filter {PIN_NAME =~ *CE} -of_objects [get_cells *pulse_height_reg*]]]