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infra: add sample makefile

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Phil
2026-04-28 14:41:56 +03:00
parent 5f1f4e5a16
commit d5c3ff873f
4 changed files with 51 additions and 308 deletions
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51
rtl/sampler/tests/Makefile Normal file
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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# FPGA settings
FPGA_PART = xc7a35tfgg484-1
FPGA_TOP = sampler
FPGA_ARCH = artix7
RTL_DIR = ../src
include ../../../scripts/vivado.mk
SYN_FILES += $(sort $(shell find ../src -type f \( -name '*.v' -o -name '*.sv' \)))
XCI_FILES = $(sort $(shell find ../src -type f -name '*.xci'))
XDC_FILES += ../../../constraints/ax7a035b.xdc
SYN_FILES += sampler_main_tb.sv
SIM_TOP = sampler_tb
program: $(PROJECT).bit
echo "open_hw_manager" > program.tcl
echo "connect_hw_server" >> program.tcl
echo "open_hw_target" >> program.tcl
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
echo "program_hw_devices [current_hw_device]" >> program.tcl
echo "exit" >> program.tcl
vivado -nojournal -nolog -mode batch -source program.tcl
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
echo "exit" >> generate_mcs.tcl
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
mkdir -p rev
COUNT=100; \
while [ -e rev/$*_rev$$COUNT.bit ]; \
do COUNT=$$((COUNT+1)); done; \
COUNT=$$((COUNT-1)); \
for x in .mcs .prm; \
do cp $*$$x rev/$*_rev$$COUNT$$x; \
echo "Output: rev/$*_rev$$COUNT$$x"; done;

121
rtl/sampler/tests/sampler_tb.sv
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`timescale 1ns / 1ps
module sampler_tb;
parameter DATA_WIDTH = 12;
parameter PACK_FACTOR = 1;
parameter PROCESS_MODE = 0;
parameter CLK_PERIOD = 15.3846; // 65 MHz
logic clk;
logic rst;
logic [DATA_WIDTH-1:0] data_in;
logic out_of_range;
logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
logic m_axis_tvalid;
sampler #(
.DATA_WIDTH(DATA_WIDTH),
.PACK_FACTOR(PACK_FACTOR),
.PROCESS_MODE(PROCESS_MODE)
) dut (
.clk_in(clk),
.rst(rst),
.data_in(data_in),
.out_of_range(out_of_range),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid)
);
initial begin
clk = 0;
forever #(CLK_PERIOD/2) clk = ~clk;
end
task send(input [DATA_WIDTH-1:0] word, input bit oor);
@(posedge clk);
data_in <= word;
out_of_range <= oor;
$display("Send: %h (%0d) OOR=%b", word, word, oor);
endtask
initial begin
$display("\n=== SAMPLER TEST (MODE=%0d) ===\n", PROCESS_MODE);
// Reset
rst = 1;
out_of_range = 0;
data_in = 0;
// send(12'h001, 0);
repeat(5) @(posedge clk);
rst = 0;
send(12'h001, 0);
repeat(1) @(posedge clk);
// 1. Positive
$display("\n--- Positive numbers ---");
// send(12'h001, 0);
send(12'h002, 0);
send(12'h003, 0);
send(12'h004, 0);
send(12'h005, 0);
send(12'h806, 0);
// 2. Negative
$display("\n--- Negative numbers ---");
send(12'hFFF, 0); // -1
send(12'hFFE, 0); // -2
send(12'hFFD, 0); // -3
send(12'h800, 0); // -2048
send(12'h801, 0); // -2047
send(12'h802, 0); // -2046
// 3. Boundary
$display("\n--- Boundary values ---");
send(12'h000, 0); // 0
send(12'h001, 0); // 1
send(12'h7FF, 0); // 2047 (max positive)
send(12'h7FE, 0); // 2046
send(12'h800, 0); // -2048 (min negative)
send(12'hFFF, 0); // -1
// 4. Out of range tests
$display("\n--- Out of range tests ---");
send(12'h00A, 0);
send(12'h00B, 1); //
send(12'h00C, 0);
send(12'h00D, 0);
send(12'h00E, 0);
send(12'h00F, 0);
send(12'h010, 0);
send(12'h011, 0);
send(12'h012, 1); //
send(12'h013, 0);
send(12'h014, 0);
send(12'h015, 0);
repeat(10) @(posedge clk);
$display("\n=== TEST FINISHED ===");
$finish;
end
// Results
// always @(posedge clk) begin
// if (m_axis_tvalid) begin
// $display("\n>>> PACKET RECEIVED at %0t ns:", $time);
// $display(" Full: %h", m_axis_tdata);
// $display(" Word0: %h", m_axis_tdata[11:0]);
// $display(" Word1: %h", m_axis_tdata[23:12]);
// $display(" Word2: %h\n", m_axis_tdata[35:24]);
// end
// end
endmodule

120
rtl/sampler/tests/sampler_tb_advanced.sv
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`timescale 1ns / 1ps
module sampler_tb;
parameter DATA_WIDTH = 12;
parameter PACK_FACTOR = 3;
parameter PROCESS_MODE = 1;
parameter CLK_PERIOD = 15.3846; // 65 MHz
logic clk;
logic rst;
logic [DATA_WIDTH-1:0] data_in;
logic out_of_range;
logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
logic m_axis_tvalid;
sampler #(
.DATA_WIDTH(DATA_WIDTH),
.PACK_FACTOR(PACK_FACTOR),
.PROCESS_MODE(PROCESS_MODE)
) dut (
.clk_in(clk),
.rst(rst),
.data_in(data_in),
.out_of_range(out_of_range),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid)
);
initial begin
clk = 0;
forever #(CLK_PERIOD/2) clk = ~clk;
end
task send(input [DATA_WIDTH-1:0] word, input bit oor);
@(posedge clk);
data_in <= word;
out_of_range <= oor;
$display("Send: %h (%0d) OOR=%b", word, word, oor);
endtask
initial begin
$display("\n=== SAMPLER TEST (MODE=%0d) ===\n", PROCESS_MODE);
// Reset
rst = 1;
out_of_range = 0;
data_in = 0;
// send(12'h001, 0);
repeat(5) @(posedge clk);
rst = 0;
send(12'h001, 0);
repeat(1) @(posedge clk);
// 1. Positive
$display("\n--- Positive numbers ---");
// send(12'h001, 0);
send(12'h002, 0);
send(12'h003, 0);
send(12'h004, 0);
send(12'h005, 0);
send(12'h806, 0);
// 2. Negative
$display("\n--- Negative numbers ---");
send(12'hFFF, 0); // -1
send(12'hFFE, 0); // -2
send(12'hFFD, 0); // -3
send(12'h800, 0); // -2048
send(12'h801, 0); // -2047
send(12'h802, 0); // -2046
// 3. Boundary
$display("\n--- Boundary values ---");
send(12'h000, 0); // 0
send(12'h001, 0); // 1
send(12'h7FF, 0); // 2047 (max positive)
send(12'h7FE, 0); // 2046
send(12'h800, 0); // -2048 (min negative)
send(12'hFFF, 0); // -1
// 4. Out of range tests
$display("\n--- Out of range tests ---");
send(12'h00A, 0);
send(12'h00B, 1); //
send(12'h00C, 0);
send(12'h00D, 0);
send(12'h00E, 0);
send(12'h00F, 0);
send(12'h010, 0);
send(12'h011, 0);
send(12'h012, 1); //
send(12'h013, 0);
send(12'h014, 0);
send(12'h015, 0);
repeat(10) @(posedge clk);
$display("\n=== TEST FINISHED ===");
$finish;
end
// Results
always @(posedge clk) begin
if (m_axis_tvalid) begin
$display("\n>>> PACKET RECEIVED at %0t ns:", $time);
$display(" Full: %h", m_axis_tdata);
$display(" Word0: %h", m_axis_tdata[11:0]);
$display(" Word1: %h", m_axis_tdata[23:12]);
$display(" Word2: %h\n", m_axis_tdata[35:24]);
end
end
endmodule

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rtl/sampler/tests/sampler_tb_basic.sv
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`timescale 1ns / 1ps
module sampler_tb;
parameter DATA_WIDTH = 12;
parameter PACK_FACTOR = 3;
parameter PROCESS_MODE = 0;
parameter CLK_PERIOD = 15.3846;
logic clk;
logic rst;
logic [DATA_WIDTH-1:0] data_in;
logic out_of_range;
logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
logic m_axis_tvalid;
// DUT
sampler #(
.DATA_WIDTH(DATA_WIDTH),
.PACK_FACTOR(PACK_FACTOR),
.PROCESS_MODE(PROCESS_MODE)
) dut (
.clk_in(clk),
.rst(rst),
.data_in(data_in),
.out_of_range(out_of_range),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid)
);
// clock
initial begin
clk = 0;
forever #(CLK_PERIOD/2) clk = ~clk;
end
integer i;
initial begin
clk = 0;
rst = 1;
data_in = 0;
out_of_range = 0;
#20;
rst = 0;
repeat(5) @(posedge clk);
for (i = 1; i < 20; i++) begin
@(posedge clk);
data_in <= i;
end
#50;
$finish;
end
always @(posedge clk) begin
if (m_axis_tvalid) begin
$display("TIME=%0t PACKED DATA = %h", $time, m_axis_tdata);
end
end
endmodule