From d26bc2950774e2eb540db45160e9302dd0aa60bc Mon Sep 17 00:00:00 2001 From: otroubi Date: Wed, 6 May 2026 14:40:33 +0300 Subject: [PATCH] rtl: debug synchronizer project --- designs/adc_dac_synchoronizer/sync_top.sv | 137 ++++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100644 designs/adc_dac_synchoronizer/sync_top.sv diff --git a/designs/adc_dac_synchoronizer/sync_top.sv b/designs/adc_dac_synchoronizer/sync_top.sv new file mode 100644 index 0000000..e2ae3f7 --- /dev/null +++ b/designs/adc_dac_synchoronizer/sync_top.sv @@ -0,0 +1,137 @@ +`timescale 1ns / 1ps + +module sync_top +#( + parameter int unsigned DAC_DATA_WIDTH = 14, + parameter int unsigned ADC_DATA_WIDTH = 12, + parameter int unsigned PACK_FACTOR = 1, + parameter int unsigned PROCESS_MODE = 0 +) +( + input adc_clk_in, + input adc_rst, + + input dac_clk_in, + input dac_rst, + + input dac_start, + + input [31:0] pulse_width, + input [31:0] pulse_period, + input [DAC_DATA_WIDTH-1:0] pulse_height, + input [15:0] pulse_num, + input [31:0] smp_num, + + output logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata, + output logic m_axis_tvalid +); + + //------------------------------------------------------------ + // Internal signals + //------------------------------------------------------------ + (* MARK_DEBUG="true" *) logic start_sampler; + + (* MARK_DEBUG="true" *) logic sample_req; + (* MARK_DEBUG="true" *) logic sample_req_sync1; + (* MARK_DEBUG="true" *) logic sample_req_sync2; + (* MARK_DEBUG="true" *) logic sample_req_sync3; + + (* MARK_DEBUG="true" *) logic sample_done; + (* MARK_DEBUG="true" *) logic sample_done_sync1; + (* MARK_DEBUG="true" *) logic sample_done_sync2; + (* MARK_DEBUG="true" *) logic sample_done_sync3; + + (* MARK_DEBUG="true" *) logic pulse; + (* MARK_DEBUG="true" *) logic [DAC_DATA_WIDTH-1:0] pulse_height_out; + + //------------------------------------------------------------ + // Simple DAC -> ADC test source + // + // generator output is directly connected to sampler input + // with width truncation: + // + // pulse_height_out[13:0] -> data_in[11:0] + //------------------------------------------------------------ + (* MARK_DEBUG="true" *) logic [ADC_DATA_WIDTH-1:0] data_in; + (* MARK_DEBUG="true" *) logic out_of_range; + + assign data_in = pulse_height_out[ADC_DATA_WIDTH-1:0]; + assign out_of_range = 1'b0; + + //------------------------------------------------------------ + // DAC -> ADC CDC + //------------------------------------------------------------ + always_ff @(posedge adc_clk_in or posedge adc_rst) begin + if (adc_rst) begin + sample_req <= 1'b0; + sample_req_sync2 <= 1'b0; + sample_req_sync3 <= 1'b0; + end + else begin + sample_req_sync2 <= sample_req_sync1; + sample_req_sync3 <= sample_req_sync2; + sample_req <= sample_req_sync3; + end + end + + //------------------------------------------------------------ + // ADC -> DAC CDC + //------------------------------------------------------------ + always_ff @(posedge dac_clk_in or posedge dac_rst) begin + if (dac_rst) begin + sample_done <= 1'b0; + sample_done_sync2 <= 1'b0; + sample_done_sync3 <= 1'b0; + end + else begin + sample_done_sync2 <= sample_done_sync1; + sample_done_sync3 <= sample_done_sync2; + sample_done <= sample_done_sync3; + end + end + + //------------------------------------------------------------ + // Generator + //------------------------------------------------------------ + generator #( + .DATA_WIDTH(DAC_DATA_WIDTH) + ) generator_inst ( + .clk_in(dac_clk_in), + .rst(dac_rst), + .start(dac_start), + + .pulse_width(pulse_width), + .pulse_period(pulse_period), + .pulse_height(pulse_height), + .pulse_num(pulse_num), + + .sample_done(sample_done), + + .pulse(pulse), + .pulse_height_out(pulse_height_out), + .sample_req(sample_req_sync1) + ); + + //------------------------------------------------------------ + // Sampler + //------------------------------------------------------------ + sampler #( + .DATA_WIDTH(ADC_DATA_WIDTH), + .PACK_FACTOR(PACK_FACTOR), + .PROCESS_MODE(PROCESS_MODE) + ) sampler_inst ( + .clk_in(adc_clk_in), + .rst(adc_rst), + + .data_in(data_in), + .out_of_range(out_of_range), + + .smp_num(smp_num), + .sample_req(sample_req), + + .m_axis_tdata(m_axis_tdata), + .m_axis_tvalid(m_axis_tvalid), + .sample_done(sample_done_sync1) + ); + +endmodule \ No newline at end of file