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controller_wrapper_axil with DMA control registers

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otroubi
2026-07-14 13:07:48 +03:00
parent 19bade1c8c
commit d0f48ba513
3 changed files with 169 additions and 21 deletions
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140
rtl/controller/src/controller_wrapper_axil.sv
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@ -1,8 +1,24 @@
module controller_wrapper_axil #(
parameter int unsigned DAC_DATA_WIDTH = 12,
parameter int unsigned ADDR_W = 16,
parameter int unsigned DATA_W = 32,
parameter int unsigned USER_W = 1
parameter int unsigned AXI_ADDR_WIDTH = 16,
parameter int unsigned AXIS_ID_WIDTH = 8,
parameter int unsigned LEN_WIDTH = 20,
parameter int unsigned AXIS_USER_WIDTH = 1,
parameter int unsigned AXIS_DEST_WIDTH = 8,
parameter int unsigned TAG_WIDTH = 8,
parameter int unsigned READ_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH,
parameter int unsigned WRITE_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH,
parameter int unsigned DESC_CMD_RAW_WIDTH = READ_DESC_WIDTH + WRITE_DESC_WIDTH,
parameter int unsigned DESC_CMD_DATA_WIDTH = ((DESC_CMD_RAW_WIDTH + 7) / 8) * 8,
parameter int unsigned DESC_CMD_KEEP_WIDTH = DESC_CMD_DATA_WIDTH / 8,
parameter int unsigned READ_STATUS_WIDTH = TAG_WIDTH + 4,
parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4,
parameter int unsigned DESC_STATUS_RAW_WIDTH = READ_STATUS_WIDTH + WRITE_STATUS_WIDTH,
parameter int unsigned DESC_STATUS_DATA_WIDTH = ((DESC_STATUS_RAW_WIDTH + 7) / 8) * 8,
parameter int unsigned DESC_STATUS_KEEP_WIDTH = DESC_STATUS_DATA_WIDTH / 8,
parameter int unsigned DESC_STATUS_USER_WIDTH = 2
)
(
input logic ctrl_clk,
@ -29,10 +45,29 @@ module controller_wrapper_axil #(
output logic dac_start,
output logic adc_start,
output logic dac_rst,
output logic adc_rst
output logic adc_rst,
// AXIS DMA
input logic ready_desc_read,
input logic ready_desc_write,
output logic ready_status_read,
output logic ready_status_write,
output logic valid_desc_read,
output logic valid_desc_write,
input logic valid_status_read,
input logic valid_status_write,
input logic [READ_STATUS_WIDTH-1:0] status_read_cmd_in,
input logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd_in,
output logic [READ_DESC_WIDTH-1:0] desc_read_cmd_out,
output logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd_out
);
logic start, rst_soft, send, cfg_bus_valid, busy;
logic start, rst_soft, send_desc_read, send_desc_write, take_status_read, take_status_write, cfg_bus_valid, busy;
logic [31:0] pulse_width, pulse_period, pulse_num, pulse_height_raw, pulse_period_ADC, window_size;
logic [7:0] error_code;
logic [31:0] desc_read_addr, desc_read_len, desc_read_config, status_read;
@ -46,10 +81,10 @@ module controller_wrapper_axil #(
.clk(ctrl_clk),
.rst_n(rst_n),
.s_axil(s_axil),
// CONTROLLER ADC/ DAC
.start_o(start),
.cfg_bus_valid_o(cfg_bus_valid),
.send_o(send),
.pulse_width_o(pulse_width),
.pulse_period_o(pulse_period),
.pulse_num_o(pulse_num),
@ -57,6 +92,16 @@ module controller_wrapper_axil #(
.pulse_period_ADC_o(pulse_period_ADC),
.window_size_o(window_size),
.rst_soft_o(rst_soft),
.busy_i(busy),
.error_code_i(error_code),
// CONTROLLER DMA
.send_desc_read_o(send_desc_read),
.send_desc_write_o(send_desc_write),
.take_status_read_o(take_status_read),
.take_status_write_o(take_status_write),
.desc_read_addr_o(desc_read_addr),
.desc_read_len_o(desc_read_len),
.desc_read_config_o(desc_read_config),
@ -67,14 +112,20 @@ module controller_wrapper_axil #(
.desc_write_len_and_tag_o(desc_write_len_and_tag),
.status_write_len_i(status_write_len),
.status_write_config_i(status_write_config),
.status_write_config_i(status_write_config)
.rst_soft_o(rst_soft),
.busy_i(busy),
.error_code_i(error_code)
.desc_read_dma_busy_i(desc_read_dma_busy),
.desc_write_dma_busy_i(desc_write_dma_busy),
.status_read_dma_busy_i(status_read_dma_busy),
.status_write_dma_busy_i(status_write_dma_busy),
.desc_read_dma_hs_i(desc_read_dma_hs),
.desc_write_dma_hs_i(desc_write_dma_hs),
.status_read_dma_hs_i(status_read_dma_hs),
.status_write_dma_hs_i(status_write_dma_hs)
);
// CONTROLLER DAC ADC
// -------------------------------------------------------------------------
// Field layout inside cfg_bus:
// [31:0] pulse_width
@ -116,5 +167,68 @@ module controller_wrapper_axil #(
.adc_rst(adc_rst)
);
// CONTROLLER DMA
logic [READ_DESC_WIDTH-1:0] desc_read_cmd;
assign desc_read_cmd = { desc_read_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH+AXIS_USER_WIDTH-1:0], desc_read_len[LEN_WIDTH-1:0], desc_read_addr[AXI_ADDR_WIDTH-1:0]};
logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd;
assign desc_write_cmd = {desc_write_len_and_tag[LEN_WIDTH+TAG_WIDTH-1:0],desc_write_addr[AXI_ADDR_WIDTH-1:0]};
logic [READ_STATUS_WIDTH-1:0] status_read_cmd;
assign status_read_cmd = status_read[TAG_WIDTH+4:0];
logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd;
assign status_write_cmd = {status_write_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH+AXIS_USER_WIDTH+4:0], status_write_len[LEN_WIDTH-1:0]};
logic desc_read_dma_busy, desc_write_dma_busy, status_read_dma_busy, status_write_dma_busy;
logic desc_read_dma_hs, desc_write_dma_hs, status_read_dma_hs, status_write_dma_hs;
dma_controller
#(
.READ_DESC_WIDTH(READ_DESC_WIDTH),
.WRITE_DESC_WIDTH(WRITE_DESC_WIDTH),
.READ_STATUS_WIDTH(READ_STATUS_WIDTH),
.WRITE_STATUS_WIDTH(WRITE_STATUS_WIDTH),
) dma_controller_inst
(
.dma_clk(ctrl_clk),
.rst_n(rst_n),
.send_desc_read(send_desc_read),
.send_desc_write(send_desc_write),
.take_status_read(take_status_read),
.take_status_write(take_status_write),
.desc_read_cmd(desc_read_cmd),
.desc_write_cmd(desc_write_cmd),
.status_read_cmd(status_read_cmd),
.status_write_cmd(status_write_cmd),
.desc_read_cmd_out(desc_read_cmd_out),
.desc_write_cmd_out(desc_write_cmd_out),
.status_read_cmd_in(status_read_cmd_in),
.status_write_cmd_in(status_write_cmd_in),
.ready_desc_read(ready_desc_read),
.ready_desc_write(ready_desc_write),
.ready_status_read(ready_status_read),
.ready_status_write(ready_status_write),
.valid_desc_read(valid_desc_read),
.valid_desc_write(valid_desc_write),
.valid_status_read(valid_status_read),
.valid_status_write(valid_status_write),
.desc_read_dma_busy(desc_read_dma_busy),
.desc_write_dma_busy(desc_write_dma_busy),
.status_read_dma_busy(status_read_dma_busy),
.status_write_dma_busy(status_write_dma_busy),
.desc_read_dma_hs(desc_read_dma_hs),
.desc_write_dma_hs(desc_write_dma_hs),
.status_read_dma_hs(status_read_dma_hs),
.status_write_dma_hs(status_write_dma_hs)
);
endmodule