random config tests
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@ -68,10 +68,10 @@ module generator
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dac_out <= pulse_height_reg;
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dac_out <= pulse_height_reg;
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else
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else
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dac_out <= ZERO_LEVEL;
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dac_out <= ZERO_LEVEL;
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cnt_pulse_period <= cnt_pulse_period + 1;
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cnt_pulse_period++;
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end
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end
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else if (cnt_pulse_period == pulse_period_reg) begin
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else if (cnt_pulse_period == pulse_period_reg) begin
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cnt_pulse_num <= cnt_pulse_num + 1;
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cnt_pulse_num++;
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cnt_pulse_period <= 0;
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cnt_pulse_period <= 0;
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synced <= 0;
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synced <= 0;
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dac_out <= ZERO_LEVEL;
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dac_out <= ZERO_LEVEL;
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@ -24,6 +24,15 @@ module generator_tb;
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wire [DATA_WIDTH-1:0] dac_out; // DAC input logic signal
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wire [DATA_WIDTH-1:0] dac_out; // DAC input logic signal
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wire generator_done; // generator request for synchronization
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wire generator_done; // generator request for synchronization
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// === Переменные ===
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int current_zero_level;
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initial begin
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if (ZERO_LEVEL == "true")
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current_zero_level = VOLTAGE_ZERO_LEVEL;
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else
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current_zero_level = LOGIC_ZERO_LEVEL;
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end
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// DUT
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// DUT
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generate
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generate
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if (ZERO_LEVEL == "true") begin : gen_dut_true
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if (ZERO_LEVEL == "true") begin : gen_dut_true
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@ -202,19 +211,73 @@ module generator_tb;
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end
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end
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end
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end
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join
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join
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repeat(pulse_p) @(posedge clk);
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repeat(pulse_p+5) @(posedge clk);
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disable counter_proc;
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disable counter_proc;
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// Ожидание завершения переходных процессов
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// Ожидание завершения переходных процессов
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repeat(10) @(posedge clk);
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repeat(10) @(posedge clk);
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if (total_impulse_cycles == pulse_w*pulse_n)
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if (total_impulse_cycles == pulse_w*pulse_n)
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$display("[TB] -check_impulses- Pulse generation correct");
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$display("[TB] -check_impulses- Pulse generation CORRECT");
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else begin
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else begin
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$display("[ERROR] -check_impulses- Pulse generation incorrect. Total number of pulses: %d, must be: %d", total_impulse_cycles, pulse_w*pulse_n);
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$display("[ERROR] -check_impulses- Pulse generation INCORRECT. Total number of pulses: %d, must be: %d", total_impulse_cycles, pulse_w*pulse_n);
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$finish;
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$finish;
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end
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end
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$display("[TB] -check_impulses- Done");
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$display("[TB] -check_impulses- Done");
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endtask
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endtask
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task automatic run_test_case(
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input int pulse_w,
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input int pulse_p,
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input int pulse_n,
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input int pulse_h,
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input bit skip_reset
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);
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int total_impulse_cycles = 0;
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if (!skip_reset) begin
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reset_dut(1);
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@(posedge clk);
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end
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set_config(
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.w(pulse_w),
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.p(pulse_p),
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.n(pulse_n),
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.h(pulse_h)
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);
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@(posedge clk);
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start_dut(1);
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// Фоновый процесс подсчета тактов импульса
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fork
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begin : counter_proc
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forever begin
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@(posedge dac_wrt);
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if (dac_out == pulse_h) begin
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total_impulse_cycles++;
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end
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end
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end
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join_none
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repeat(pulse_n) begin
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synchronize(
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.sampler_first(0),
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.delay_before_ack(1),
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.ack_duration(2)
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);
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end
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repeat(pulse_p+5) @(posedge clk);
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disable counter_proc;
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repeat(10) @(posedge clk);
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if (total_impulse_cycles == pulse_w*pulse_n)
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$display("[TB] -run_test_case- Pulse generation CORRECT");
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else begin
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$display("[ERROR] -run_test_case- Pulse generation INCORRECT. Total number of pulses: %d, must be: %d", total_impulse_cycles, pulse_w*pulse_n);
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$finish;
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end
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endtask
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// --- ОСНОВНОЙ ПРОЦЕСС ТЕСТИРОВАНИЯ ---
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// --- ОСНОВНОЙ ПРОЦЕСС ТЕСТИРОВАНИЯ ---
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initial begin
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initial begin
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@ -229,7 +292,39 @@ module generator_tb;
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pulse_num = 0;
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pulse_num = 0;
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sampler_done = 0;
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sampler_done = 0;
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$display("[TB] Test 1. Random latency for control signals");
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check_impulses();
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check_impulses();
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$display("[TB] Test 1 complete");
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$display("[TB] Test 2. Random configs");
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for (int i = 0; i < 25; i++) begin
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int r_w, r_p, r_n, r_h;
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bit r_skip;
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// Генерируем параметры
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r_p = $urandom_range(5, 50); // Период от 5 до 50
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r_w = $urandom_range(0, r_p); // Ширина не больше периода
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r_n = $urandom_range(1, 10); // Количество импульсов
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r_h = $urandom_range(1, 2**DATA_WIDTH-1); // Высота (для 14 бит)
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r_skip = $urandom_range(0, 1); // Случайный сброс (0 - сброс, 1 - пропуск)
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// Защита от "нулевого" импульса. Невозможно проверить длительность.
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if (r_h == current_zero_level) begin
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r_h += $urandom_range(1, 10);
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end
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$display("[TB] --- Test #%0d (Config: W=%0d, P=%0d, N=%0d, H=%0d, SkipReset=%0b) ---",
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i+1, r_w, r_p, r_n, r_h, r_skip);
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run_test_case(
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.pulse_w(r_w),
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.pulse_p(r_p),
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.pulse_n(r_n),
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.pulse_h(r_h),
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.skip_reset(r_skip)
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);
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end
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$display("[TB] Test 2 complete");
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$display("[TB] All Tests complete!");
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$display("[TB] All Tests complete!");
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$finish;
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$finish;
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