half-baked new generator

rtl/generator/src/generator.sv

@@ -1,54 +1,48 @@
 `timescale 1ns / 1ps
 
-
 module generator
 #(
     parameter DATA_WIDTH = 14,
     parameter ZERO_LEVEL = 8192 // 8192 or 0
-    )
+)
 (
-    input clk_in,
+    input clk_dac,
     input rst,
     input start,
     input [31:0]           pulse_width,
     input [31:0]           pulse_period,
     input [DATA_WIDTH-1:0] pulse_height,
     input [15:0]           pulse_num,
-    input sample_done,
+    input request,
     
-    output pulse,
+    output dac_wrt,
-    output[DATA_WIDTH-1:0] pulse_height_out,
+    output logic [DATA_WIDTH-1:0] dac_out,
-    output logic sample_req
+    output logic done
+);
+    logic [DATA_WIDTH-1:0] pulse_height_reg;
+    logic [31:0] pulse_width_reg, pulse_period_reg;
+    logic [15:0] pulse_num_reg;
     
-    );
+    logic [15:0] cnt_pulse_num;
+    logic [31:0] cnt_pulse_period;
 
-  (* MARK_DEBUG="true" *)  logic [DATA_WIDTH-1:0] pulse_height_reg, pulse_height_out_reg;
+    logic enable;
 
-  (* MARK_DEBUG="true" *)  logic [31:0] pulse_width_reg, pulse_period_reg;
+    always @(posedge clk_dac) begin
-  (* MARK_DEBUG="true" *)  logic [15:0] pulse_num_reg;
-    
-  (* MARK_DEBUG="true" *)  logic enable;
-  (* MARK_DEBUG="true" *)  logic [15:0] cnt_pulse_num;
-  (* MARK_DEBUG="true" *)  logic [31:0] cnt_period;
-
-    
-    always @(posedge clk_in) begin
         if (rst) begin
             pulse_height_reg   <=  ZERO_LEVEL;
-            pulse_height_out_reg <= ZERO_LEVEL;
+            pulse_width_reg    <=  0;
-            pulse_width_reg <= '0;
+            pulse_period_reg   <=  0;
-            pulse_period_reg <= '0;
+            pulse_num_reg      <=  0;
-            pulse_num_reg <= '0;
+            cnt_pulse_num      <=  0;
+            cnt_pulse_period   <=  0;
+            dac_out            <=  ZERO_LEVEL;
+            done               <=  0;
             enable             <=  0;
-            cnt_pulse_num <= '0;
-            cnt_period <= '0;
-            sample_req <= 0;
         end 
         else begin
             if (start & !enable) begin
-                enable <= 1'b1;
+                enable <= 1;
-                cnt_pulse_num <= '0;
-                cnt_period <= '0;
 
                 sample_req <= 1;
                 
@@ -96,11 +90,10 @@ module generator
         end
     end
 
+    // Gated DAC write signal from DAC clock. Needed for posedge
     OBUF OBUF_pulse_clk (
-        .I(clk_in),
+        .I(clk_in & enable),
         .O(pulse)
     );
     
-    assign pulse_height_out = pulse_height_out_reg;
-    
 endmodule