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fix: tricky packet check in ctrl

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Phil
2026-04-15 17:56:22 +03:00
parent ea7af4ed62
commit c41b08f539
1 changed files with 7 additions and 17 deletions
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18
rtl/controller/src/controller.sv
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@ -93,7 +93,7 @@ module control #(
// axi stream is always accepted. If packet is not needed, it is discarded.
assign s_axis_tready = 1'b1;
wire axis_hs = s_axis_tvalid & s_axis_tready;
(* MARK_DEBUG="true" *) wire axis_hs = s_axis_tvalid & s_axis_tready;
// -------------------------------------------------------------------------
// Shared 96-bit config bus in ETH domain
@ -110,7 +110,7 @@ module control #(
// [79:64] pulse_num
// [95:80] pulse_height_raw[15:0]
// -------------------------------------------------------------------------
logic [95:0] cfg_bus_eth;
(* MARK_DEBUG="true" *) logic [95:0] cfg_bus_eth;
logic [95:0] cfg_shift_eth;
// ETH-domain parser and control
@ -121,12 +121,12 @@ module control #(
ST_DISCARD = 3'd3
} eth_state_t;
eth_state_t eth_state;
(* MARK_DEBUG="true" *) eth_state_t eth_state;
logic [3:0] cfg_byte_cnt;
// Busy flag: set by START command, cleared by finish event from ADC domain
logic busy_flag_eth;
(* MARK_DEBUG="true" *) logic busy_flag_eth;
// Pending ACKs for config delivery
logic cfg_wait_dac_ack;
@ -242,22 +242,12 @@ module control #(
end else begin
unique case (s_axis_tdata)
CMD_SOFT_RESET: begin
// command packet must be exactly 1 byte
if (s_axis_tlast) begin
rst_toggle_eth <= ~rst_toggle_eth;
end else begin
eth_state <= ST_DISCARD;
end
end
CMD_START: begin
// command packet must be exactly 1 byte
if (s_axis_tlast) begin
start_toggle_eth <= ~start_toggle_eth;
busy_flag_eth <= 1'b1;
end else begin
eth_state <= ST_DISCARD;
end
end
CMD_SET_DATA: begin