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infra: add sim support to vivado.mk targets

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Phil
2026-04-14 12:30:30 +03:00
parent a3ed4919bc
commit c372dcd942
1 changed files with 33 additions and 1 deletions
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34
scripts/vivado.mk
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@ -37,7 +37,7 @@
################################################################### ###################################################################
# phony targets # phony targets
.PHONY: fpga vivado tmpclean clean distclean .PHONY: fpga vivado sim sim-gui simclean tmpclean clean distclean
# prevent make from deleting intermediate files and reports # prevent make from deleting intermediate files and reports
.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm .PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
@ -55,6 +55,14 @@ uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $
SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES))) SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES))) INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
# simulation parameters
SIM_TOP ?= $(FPGA_TOP)_tb
TB_FILES ?=
SIM_FILES ?= $(SYN_FILES) $(TB_FILES)
SIM_DEFS ?= $(DEFS)
SIM_RUNTIME ?= all
################################################################### ###################################################################
# Main Targets # Main Targets
# #
@ -149,3 +157,27 @@ $(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/imp
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \ cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \ if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
###################################################################
# Simulation targets
###################################################################
gen_ip:
echo "open_project $(PROJECT).xpr" > gen_ip.tcl
echo "generate_target all [get_ips *]" >> gen_ip.tcl
vivado -mode batch -source gen_ip.tcl
sim: $(PROJECT).xpr gen_ip
echo "open_project $(PROJECT).xpr" > run_sim.tcl
echo "add_files -fileset sim_1 $(TB_FILES)" >> run_sim.tcl
echo "set_property top $(SIM_TOP) [get_filesets sim_1]" >> run_sim.tcl
echo "update_compile_order -fileset sources_1" >> run_sim.tcl
echo "update_compile_order -fileset sim_1" >> run_sim.tcl
echo "launch_simulation" >> run_sim.tcl
echo "run all" >> run_sim.tcl
vivado -mode batch -source run_sim.tcl
simclean:
-rm -rf xsim.dir *.wdb *.pb *.jou *.log *.vcd *.ltx
-rm -f defines_sim.v