diff --git a/.gitignore b/.gitignore
index a89a8f3..b17acc9 100644
--- a/.gitignore
+++ b/.gitignore
@@ -26,4 +26,8 @@ run_sim.tcl
 *.bit
 *.xsa
 *.ltx
-*.bin
\ No newline at end of file
+*.bin
+
+# slang files
+.slang
+files.f
\ No newline at end of file
diff --git a/designs/reflectometer_base/reflectometer.sv b/designs/reflectometer_base/reflectometer.sv
index 295004d..cc8883e 100644
--- a/designs/reflectometer_base/reflectometer.sv
+++ b/designs/reflectometer_base/reflectometer.sv
@@ -3,13 +3,13 @@
 module reflectometer_top #(
     parameter int unsigned DAC_DATA_WIDTH = 14,
     parameter int unsigned ADC_DATA_WIDTH = 12,
-    parameter PACK_FACTOR = 1,
-    parameter PROCESS_MODE = 0,
-    parameter ZERO_LEVEL = 8192,
-    parameter ACCUM_WIDTH = 32,
-    parameter N_MAX = 4096,
-    parameter WINDOW_SIZE = 65,
-    parameter PACKET_SIZE = 1024
+    parameter int unsigned PACK_FACTOR = 1,
+    parameter int unsigned PROCESS_MODE = 0,
+    parameter int unsigned ZERO_LEVEL = 8192,
+    parameter int unsigned ACCUM_WIDTH = 32,
+    parameter int unsigned N_MAX = 4096,
+    parameter int unsigned WINDOW_SIZE = 65,
+    parameter int unsigned PACKET_SIZE = 1024
 )(
     input               sys_clk,
     input               rst_n,
@@ -35,27 +35,19 @@ module reflectometer_top #(
     (* MARK_DEBUG="true" *) output logic       send_req,
 
     // DAC
-
-    output wire p2_clk,
-    (* MARK_DEBUG="true" *) output     wire [DAC_DATA_WIDTH-1:0]       p2_data,
-    (* MARK_DEBUG="true" *) output     wire p2_wrt,
+    output  logic                       dac_clk_o,
+    output  logic [DAC_DATA_WIDTH-1:0]  dac_data,
+    output  logic                       dac_wrt,
 
     // ADC
-    output ch2_clk,
-    (* MARK_DEBUG="true" *) input [ADC_DATA_WIDTH-1:0] ch2_data,
-    input ch2_otr
+    output  logic                       adc_clk_o,
+    input   wire [ADC_DATA_WIDTH-1:0]   adc_data,
+    input   wire                        adc_otr
 
 );
 
-    // -------------------------------------------------------------------------
-    // IDELAYCTRL
-    // -------------------------------------------------------------------------
-    (* IODELAY_GROUP = "rgmii_idelay_group" *)
-    IDELAYCTRL IDELAYCTRL_inst (
-        .RDY    (),
-        .REFCLK (sys_clk),
-        .RST    (1'b0)
-    );
+    wire [ADC_DATA_WIDTH*PACK_FACTOR-1:0] sampler_m_axis_tdata;
+    wire                                  sampler_m_axis_tvalid;
 
     // -------------------------------------------------------------------------
     // Generated clocks for controller
@@ -68,12 +60,18 @@ module reflectometer_top #(
     wire adc_clk;
     wire clk_wiz_locked;
 
-    clk_wiz_ctrl_inst clk_wiz_ctrl_inst (
-        .clk_in1   (sys_clk),
-        .reset    (~rst_n),
-        .clk_out1  (dac_clk),   // 130 MHz
-        .clk_out2  (adc_clk),   // 65 MHz
-        .locked    (clk_wiz_locked)
+    clk_wiz_ctrl_inst clock_wiz_inst
+    (
+        // Clock in ports
+        .clk_200(clk_in),
+        // Clock out ports  
+        .clk_adc_65(clk_adc),
+        .clk_adc_65_180(clk_sampler),
+        .clk_dac_125(clk_dac),
+        .clk_dac_125_180(clk_generator),
+        // Status and control signals               
+        .resetn(rst_n), 
+        .locked(clk_locked)
     );
 
     // -------------------------------------------------------------------------
@@ -87,7 +85,7 @@ module reflectometer_top #(
     // Controller reset
     // Use both external reset and clk_wiz lock
     // -------------------------------------------------------------------------
-    wire ctrl_rst_n = rst_n & clk_wiz_locked;
+    wire ctrl_rst_n = rst_n & clk_locked;
 
 
     (* MARK_DEBUG="true" *) logic        finish;
@@ -262,15 +260,13 @@ module reflectometer_top #(
         .DATA_WIDTH(ADC_DATA_WIDTH),
         .PACK_FACTOR(PACK_FACTOR),
         .PROCESS_MODE(PROCESS_MODE)
-    )
-    sampler_dut
-    (
-       .clk_in(adc_clk),
-       .rst(adc_rst),
-       .data_in(ch2_data),
-       .out_of_range(ch2_otr),
-       .m_axis_tdata(accum_m_axis_tdata),
-       .m_axis_tvalid(acum_m_axis_tvalid),
+    ) sampler_dut (
+        .clk_in(clk_sampler),
+        .rst(adc_rst),
+        .data_in(adc_data),
+        .out_of_range(adc_otr),
+        .m_axis_tdata(sampler_m_axis_tdata),
+        .m_axis_tvalid(sampler_m_axis_tvalid),
         .smp_num(adc_pulse_period),
         .sample_req(sample_req),
         .sample_done(sample_done_sync1)
@@ -313,8 +309,9 @@ module reflectometer_top #(
     // -------------------------------------------------------------------------
     // Simple LED status
     // -------------------------------------------------------------------------
-    assign led[0] = clk_wiz_locked;
-    assign led[1] = m_axis_rx_tvalid;
-    assign led[2] = dac_start;
+    assign status_led[0] = rst_n;
+    assign status_led[1] = clk_locked;
+    // assign status_led[2] = ;
+    // assign status_led[3] = ;
 
-endmodule
\ No newline at end of file
+endmodule