transferring test for controller dma ram connective
This commit is contained in:
otroubi
@@ -0,0 +1,48 @@
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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PWD := $(shell pwd)
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WRAP_DIR = $(PWD)/../src
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RTL_DIR = $(PWD)/../../controller/src
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LIBS_DIR = $(PWD)/../../../external/rtl_libs
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VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_pkg.sv
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VERILOG_SOURCES += $(RTL_DIR)/dma_reg_pkg.sv
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VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_if.sv
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VERILOG_SOURCES += $(LIBS_DIR)/axi/axi_reg/axi4l_reg_map.sv
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VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_rd.v
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VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_wr.v
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VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma.v
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VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_ram.v
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VERILOG_SOURCES += $(RTL_DIR)/axi_ram_wrapper.sv
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VERILOG_SOURCES += $(RTL_DIR)/controller.sv
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VERILOG_SOURCES += $(RTL_DIR)/dma_controller.sv
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VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_desc.sv
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VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_status.sv
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VERILOG_SOURCES += $(RTL_DIR)/controller_wrapper_axil.sv
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VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller_pkg.sv
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VERILOG_SOURCES += $(RTL_DIR)/axis_defaults_helper.sv
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VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller.sv
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VERILOG_SOURCES += $(WRAP_DIR)/wrapper_controller_dma.sv
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VERILOG_SOURCES += $(WRAP_DIR)/axi_dma_wrapper_if.sv
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VERILOG_SOURCES += $(PWD)/tb_controller_dma_wrapper_axil.sv
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TOPLEVEL = tb_controller_dma_wrapper_axil
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MODULE = test_controller_and_dma
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ifeq ($(SIM),verilator)
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EXTRA_ARGS += --trace --trace-structs
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EXTRA_ARGS += -I$(LIBS_DIR)/axi/rtl/
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COMPILE_ARGS += -Wno-fatal
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COMPILE_ARGS += -I$(LIBS_DIR)/axi/rtl/
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EXTRA_ARGS += --trace
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EXTRA_ARGS += --trace-structs
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EXTRA_ARGS += --public-flat-rw
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EXTRA_ARGS += -Wno-fatal
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EXTRA_ARGS += --timing
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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@@ -0,0 +1,298 @@
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import dma_reg_pkg::*;
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module tb_controller_wrapper_axil #(
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parameter int unsigned ADDR_W = 16,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1,
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parameter int unsigned DAC_DATA_WIDTH = 12,
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parameter int unsigned AXI_DATA_WIDTH = 32,
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parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
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parameter int unsigned AXI_ID_WIDTH = 8,
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parameter int unsigned AXI_USER_WIDTH = 1,
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parameter int unsigned AXI_MAX_BURST_LEN = 16,
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parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
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parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
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parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
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parameter int unsigned AXIS_LAST_ENABLE = 1,
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parameter int unsigned AXIS_ID_ENABLE = 1,
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parameter int unsigned AXIS_DEST_ENABLE = 0,
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parameter int unsigned AXIS_USER_ENABLE = 1,
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parameter int unsigned ENABLE_SG = 0,
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parameter int unsigned ENABLE_UNALIGNED = 0
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)(
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input logic ctrl_clk,
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input logic rst,
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input logic [ADDR_W-1:0] s_axil_awaddr,
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input logic [2:0] s_axil_awprot,
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input logic s_axil_awvalid,
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output logic s_axil_awready,
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input logic [DATA_W-1:0] s_axil_wdata,
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input logic [DATA_W/8-1:0] s_axil_wstrb,
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input logic s_axil_wvalid,
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output logic s_axil_wready,
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output logic [1:0] s_axil_bresp,
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output logic s_axil_bvalid,
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input logic s_axil_bready,
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input logic [ADDR_W-1:0] s_axil_araddr,
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input logic [2:0] s_axil_arprot,
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input logic s_axil_arvalid,
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output logic s_axil_arready,
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output logic [DATA_W-1:0] s_axil_rdata,
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output logic [1:0] s_axil_rresp,
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output logic s_axil_rvalid,
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input logic s_axil_rready,
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep,
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input wire s_axis_write_data_tvalid,
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output wire s_axis_write_data_tready,
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input wire s_axis_write_data_tlast,
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input wire [AXIS_ID_WIDTH-1:0] s_axis_write_data_tid,
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input wire [AXIS_DEST_WIDTH-1:0] s_axis_write_data_tdest,
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input wire [AXIS_USER_WIDTH-1:0] s_axis_write_data_tuser,
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output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep,
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output wire m_axis_read_data_tvalid,
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input wire m_axis_read_data_tready,
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output wire m_axis_read_data_tlast,
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output wire [AXIS_ID_WIDTH-1:0] m_axis_read_data_tid,
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output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest,
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output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser,
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output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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output wire m_axi_awlock,
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output wire [3:0] m_axi_awcache,
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output wire [2:0] m_axi_awprot,
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output wire m_axi_awvalid,
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input wire m_axi_awready,
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output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
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output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
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output wire m_axi_wlast,
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output wire m_axi_wvalid,
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input wire m_axi_wready,
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input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
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input wire [1:0] m_axi_bresp,
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input wire m_axi_bvalid,
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output wire m_axi_bready,
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output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [7:0] m_axi_arlen,
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output wire [2:0] m_axi_arsize,
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output wire [1:0] m_axi_arburst,
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output wire m_axi_arlock,
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output wire [3:0] m_axi_arcache,
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output wire [2:0] m_axi_arprot,
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output wire m_axi_arvalid,
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input wire m_axi_arready,
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input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
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input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
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input wire [1:0] m_axi_rresp,
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input wire m_axi_rlast,
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input wire m_axi_rvalid,
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output wire m_axi_rready
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);
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logic rst_n;
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assign rst_n = ~rst;
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// Для минимального теста держим все clock domain-ы на одном clock.
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logic dac_clk_in;
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logic adc_clk_in;
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assign dac_clk_in = ctrl_clk;
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assign adc_clk_in = ctrl_clk;
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logic finish;
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assign finish = 1'b0;
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// ---------------------------------------------------------------------------
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// AXI-Lite flat -> axi4l_if
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// ---------------------------------------------------------------------------
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axi4l_if #(
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W)
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) axil_bus (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axi4l_flat_to_if #(
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W)
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) u_axil_flat_to_if (
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.s_axil_awaddr (s_axil_awaddr),
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.s_axil_awprot (s_axil_awprot),
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.s_axil_awvalid(s_axil_awvalid),
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.s_axil_awready(s_axil_awready),
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.s_axil_wdata (s_axil_wdata),
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.s_axil_wstrb (s_axil_wstrb),
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.s_axil_wvalid (s_axil_wvalid),
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.s_axil_wready (s_axil_wready),
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.s_axil_bresp (s_axil_bresp),
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.s_axil_bvalid (s_axil_bvalid),
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.s_axil_bready (s_axil_bready),
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.s_axil_araddr (s_axil_araddr),
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.s_axil_arprot (s_axil_arprot),
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.s_axil_arvalid(s_axil_arvalid),
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.s_axil_arready(s_axil_arready),
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.s_axil_rdata (s_axil_rdata),
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.s_axil_rresp (s_axil_rresp),
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.s_axil_rvalid (s_axil_rvalid),
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.s_axil_rready (s_axil_rready),
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.m_axil(axil_bus)
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);
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// ---------------------------------------------------------------------------
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// AXIS interfaces for the updated controller_wrapper_axil
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// ---------------------------------------------------------------------------
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// AXIS READ DMA MASTER output
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axis_if #(
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.DATA_W (AXIS_DATA_WIDTH),
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.KEEP_W (AXIS_KEEP_WIDTH),
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.ID_W (AXIS_ID_WIDTH),
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.DEST_W (AXIS_DEST_WIDTH),
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.USER_W (AXIS_USER_WIDTH)
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) dma_read_data (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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logic [AXIS_KEEP_WIDTH-1:0] unused_read_tstrb;
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axis_if_to_flat #(
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.DATA_W (AXIS_DATA_WIDTH),
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.KEEP_W (AXIS_KEEP_WIDTH),
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.ID_W (AXIS_ID_WIDTH),
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.DEST_W (AXIS_DEST_WIDTH),
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.USER_W (AXIS_USER_WIDTH)
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) u_read_data_if_to_flat (
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.s_axis(dma_read_data),
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.m_axis_tdata (m_axis_read_data_tdata),
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.m_axis_tkeep (m_axis_read_data_tkeep),
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.m_axis_tstrb (unused_read_tstrb),
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.m_axis_tlast (m_axis_read_data_tlast),
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.m_axis_tid (m_axis_read_data_tid),
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.m_axis_tdest (m_axis_read_data_tdest),
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.m_axis_tuser (m_axis_read_data_tuser),
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.m_axis_tvalid(m_axis_read_data_tvalid),
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.m_axis_tready(m_axis_read_data_tready)
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);
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// AXIS WRITE DMA SLAVE input
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axis_if #(
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.DATA_W (AXIS_DATA_WIDTH),
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.KEEP_W (AXIS_KEEP_WIDTH),
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.ID_W (AXIS_ID_WIDTH),
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.DEST_W (AXIS_DEST_WIDTH),
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.USER_W (AXIS_USER_WIDTH)
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) dma_write_data (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axis_flat_to_if #(
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.DATA_W (AXIS_DATA_WIDTH),
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.KEEP_W (AXIS_KEEP_WIDTH),
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.ID_W (AXIS_ID_WIDTH),
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.DEST_W (AXIS_DEST_WIDTH),
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.USER_W (AXIS_USER_WIDTH)
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) u_write_data_flat_to_if (
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.s_axis_tdata (s_axis_write_data_tdata),
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.s_axis_tkeep (s_axis_write_data_tkeep),
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.s_axis_tstrb (s_axis_write_data_tkeep),
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.s_axis_tlast (s_axis_write_data_tlast),
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.s_axis_tid (s_axis_write_data_tid),
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.s_axis_tdest (s_axis_write_data_tdest),
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.s_axis_tuser (s_axis_write_data_tuser),
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.s_axis_tvalid(s_axis_write_data_tvalid),
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.s_axis_tready(s_axis_write_data_tready),
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.m_axis(dma_write_data)
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);
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// Controller ADC/DAC outputs.
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logic [31:0] adc_window_size;
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logic [31:0] dac_pulse_width;
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logic [31:0] dac_pulse_period;
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logic [DAC_DATA_WIDTH-1:0] dac_pulse_height;
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logic [15:0] dac_pulse_num;
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logic [31:0] adc_pulse_period;
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logic [15:0] adc_pulse_num;
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logic dac_start;
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logic adc_start;
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logic dac_rst;
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logic adc_rst;
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wrapper_controller_dma #(
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W),
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
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.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
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.AXI_ID_WIDTH(AXI_ID_WIDTH),
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.AXI_USER_WIDTH(AXI_USER_WIDTH),
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.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
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.AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
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.AXIS_ID_ENABLE(AXIS_ID_ENABLE),
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.AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
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.AXIS_USER_ENABLE(AXIS_USER_ENABLE),
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.ENABLE_SG(ENABLE_SG),
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.ENABLE_UNALIGNED(ENABLE_UNALIGNED)
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) dut (
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.ctrl_clk(ctrl_clk),
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.dac_clk_in(dac_clk_in),
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.adc_clk_in(adc_clk_in),
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.rst_n(rst_n),
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.s_axil(axil_bus),
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.finish(finish),
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.adc_window_size(adc_window_size),
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.dac_pulse_width(dac_pulse_width),
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.dac_pulse_period(dac_pulse_period),
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.dac_pulse_height(dac_pulse_height),
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.dac_pulse_num(dac_pulse_num),
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.adc_pulse_period(adc_pulse_period),
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.adc_pulse_num(adc_pulse_num),
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.dac_start(dac_start),
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.adc_start(adc_start),
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.dac_rst(dac_rst),
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.adc_rst(adc_rst),
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.m_axis_read_data(dma_read_data),
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.s_axis_write_data(dma_write_data)
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);
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endmodule : tb_controller_wrapper_axil
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@@ -0,0 +1,194 @@
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotbext.axi import AxiLiteBus, AxiLiteMaster
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from cocotbext.axi import AxiBus, AxiRam, AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
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# Register indexes from axi4l_reg_map_controller_pkg.sv
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REG_CONTROL = 0
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REG_STATUS = 1
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REG_DAC_WIDTH = 2
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REG_DAC_PERIOD = 3
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REG_DAC_PULSE_NUM = 4
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REG_DAC_PULSE_HEIGHT = 5
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REG_ADC_PERIOD = 6
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REG_WINDOW_SIZE = 7
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REG_ERROR = 8
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REG_DESC_READ_ADDR = 9
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REG_DESC_READ_LEN = 10
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REG_DESC_READ_CONFIG = 11
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REG_READ_STATUS = 12
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REG_DESC_WRITE_ADDR = 13
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REG_DESC_WRITE_LEN_AND_TAG = 14
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REG_STATUS_WRITE_LEN = 15
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REG_STATUS_WRITE_CONFIG = 16
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# REG_CONTROL pulse bits
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CTRL_START = 0
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CTRL_RST_SOFT = 1
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CTRL_CFG_BUS_VALID = 2
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CTRL_SEND_DESC_READ = 3
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CTRL_SEND_DESC_WRITE = 4
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CTRL_TAKE_STATUS_READ = 5
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CTRL_TAKE_STATUS_WRITE = 6
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def reg_addr(reg_index: int) -> int:
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# AXI-Lite uses byte addresses, 32-bit registers are spaced by 4 bytes.
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return reg_index * 4
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def u32(value: int) -> bytes:
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return int(value & 0xFFFFFFFF).to_bytes(4, "little")
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class TB:
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def __init__(self, dut):
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self.dut = dut
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cocotb.start_soon(Clock(dut.ctrl_clk, 10, units="ns").start())
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self.axil = AxiLiteMaster(
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AxiLiteBus.from_prefix(dut, "s_axil"),
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dut.ctrl_clk,
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dut.rst
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)
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self.axis_source = AxiStreamSource(
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AxiStreamBus.from_prefix(dut, "s_axis_write_data"),
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dut.ctrl_clk,
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dut.rst
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)
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self.axis_sink = AxiStreamSink(
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||||
AxiStreamBus.from_prefix(dut, "m_axis_read_data"),
|
||||
dut.ctrl_clk,
|
||||
dut.rst
|
||||
)
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.value = 1
|
||||
for _ in range(5):
|
||||
await RisingEdge(self.dut.ctrl_clk)
|
||||
|
||||
self.dut.rst.value = 0
|
||||
for _ in range(5):
|
||||
await RisingEdge(self.dut.ctrl_clk)
|
||||
|
||||
async def write_reg(self, reg_index: int, value: int):
|
||||
await self.axil.write(reg_addr(reg_index), u32(value))
|
||||
|
||||
async def read_reg(self, reg_index: int) -> int:
|
||||
resp = await self.axil.read(reg_addr(reg_index), 4)
|
||||
return int.from_bytes(bytes(resp.data), "little")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def simple_axil_write_read(dut):
|
||||
tb = TB(dut)
|
||||
await tb.reset()
|
||||
|
||||
await tb.write_reg(REG_DAC_WIDTH, 0x0000_0123)
|
||||
|
||||
value = await tb.read_reg(REG_DAC_WIDTH)
|
||||
assert value == 0x0000_0123
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def simple_controller_config_write(dut):
|
||||
tb = TB(dut)
|
||||
await tb.reset()
|
||||
|
||||
await tb.write_reg(REG_DAC_WIDTH, 0x10)
|
||||
await tb.write_reg(REG_DAC_PERIOD, 0x40)
|
||||
await tb.write_reg(REG_DAC_PULSE_NUM, 3)
|
||||
await tb.write_reg(REG_DAC_PULSE_HEIGHT, 0x7FF)
|
||||
await tb.write_reg(REG_ADC_PERIOD, 0x80)
|
||||
await tb.write_reg(REG_WINDOW_SIZE, 16)
|
||||
|
||||
assert await tb.read_reg(REG_DAC_WIDTH) == 0x10
|
||||
assert await tb.read_reg(REG_WINDOW_SIZE) == 16
|
||||
|
||||
# write data: set cfg_bus_valid signal
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_CFG_BUS_VALID)
|
||||
|
||||
# wait
|
||||
for _ in range(30):
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
|
||||
# check config
|
||||
assert int(dut.dac_pulse_width) == 0x10
|
||||
assert int(dut.dac_pulse_period) == 0x40
|
||||
assert int(dut.dac_pulse_num) == 3
|
||||
assert int(dut.dac_pulse_height) == 0x7FF
|
||||
assert int(dut.adc_pulse_period) == 0x80
|
||||
assert int(dut.adc_window_size) == 16
|
||||
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def simple_controller_start_check(dut):
|
||||
tb = TB(dut)
|
||||
await tb.reset()
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_START)
|
||||
|
||||
await RisingEdge(dut.dac_start)
|
||||
|
||||
@cocotb.test()
|
||||
async def simple_dma_mem_to_mem(dut):
|
||||
tb = TB(dut)
|
||||
await tb.reset()
|
||||
|
||||
SRC_ADDR = 0x1000
|
||||
LENGTH = 8
|
||||
|
||||
tx_data = bytes([ 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88 ])
|
||||
|
||||
## write part
|
||||
|
||||
await tb.write_reg(REG_DESC_WRITE_ADDR, SRC_ADDR)
|
||||
await tb.write_reg(REG_DESC_WRITE_LEN_AND_TAG, LENGTH)
|
||||
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_SEND_DESC_WRITE)
|
||||
|
||||
await tb.axis_source.send(AxiStreamFrame(tx_data))
|
||||
|
||||
for _ in range(20):
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_TAKE_STATUS_WRITE)
|
||||
|
||||
for _ in range(10):
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
|
||||
|
||||
assert await tb.read_reg(REG_STATUS_WRITE_CONFIG) == 0
|
||||
assert await tb.read_reg(REG_STATUS_WRITE_LEN) == 0x8
|
||||
|
||||
## read part
|
||||
|
||||
await tb.write_reg(REG_DESC_READ_ADDR, SRC_ADDR)
|
||||
await tb.write_reg(REG_DESC_READ_LEN, LENGTH)
|
||||
await tb.write_reg(REG_DESC_READ_CONFIG, 0x0000_0001)
|
||||
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_SEND_DESC_READ)
|
||||
|
||||
rx_frame = await tb.axis_sink.recv()
|
||||
|
||||
for _ in range(20):
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_TAKE_STATUS_READ)
|
||||
|
||||
for _ in range(10):
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
|
||||
assert await tb.read_reg(REG_READ_STATUS) == 0x1
|
||||
|
||||
assert bytes(rx_frame) == tx_data
|
||||
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
# Primary clocks
|
||||
create_clock -name eth_clk -period 8.000 [get_ports eth_clk_in]
|
||||
create_clock -name dac_clk -period 7.692 [get_ports dac_clk_in]
|
||||
create_clock -name adc_clk -period 15.385 [get_ports adc_clk_in]
|
||||
|
||||
|
||||
# Asynchronous clock groups
|
||||
# eth, dac, adc are independent domains
|
||||
|
||||
set_clock_groups -name ASYNC_ETH_DAC_ADC -asynchronous \
|
||||
-group [get_clocks eth_clk] \
|
||||
-group [get_clocks dac_clk] \
|
||||
-group [get_clocks adc_clk]
|
||||
Reference in New Issue
Block a user