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fix: invalid signals

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Phil
2026-07-14 20:07:23 +03:00
parent 42df57be7d
commit c057890007
2 changed files with 3 additions and 3 deletions
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4
rtl/controller/src/controller_wrapper_axil.sv
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@ -166,10 +166,10 @@ parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDT
assign desc_write_cmd = {desc_write_len_and_tag[LEN_WIDTH+TAG_WIDTH-1:0],desc_write_addr[AXI_ADDR_WIDTH-1:0]}; assign desc_write_cmd = {desc_write_len_and_tag[LEN_WIDTH+TAG_WIDTH-1:0],desc_write_addr[AXI_ADDR_WIDTH-1:0]};
logic [READ_STATUS_WIDTH-1:0] status_read_cmd, status_read_cmd_in; logic [READ_STATUS_WIDTH-1:0] status_read_cmd, status_read_cmd_in;
assign status_read_cmd = status_read[READ_STATUS_WIDTH-1:0]; assign status_read = status_read_cmd[READ_STATUS_WIDTH-1:0];
logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd, status_write_cmd_in; logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd, status_write_cmd_in;
assign status_write_cmd = {status_write_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH+AXIS_USER_WIDTH+3:0], status_write_len[LEN_WIDTH-1:0]}; assign {status_write_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH+AXIS_USER_WIDTH+3:0], status_write_len[LEN_WIDTH-1:0]} = status_write_cmd;
logic ready_desc_read, ready_desc_write, ready_status_read, ready_status_write; logic ready_desc_read, ready_desc_write, ready_status_read, ready_status_write;
logic valid_desc_read, valid_desc_write, valid_status_read, valid_status_write; logic valid_desc_read, valid_desc_write, valid_status_read, valid_status_write;

2
rtl/controller/src/dma_controller.sv
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@ -100,7 +100,7 @@ shaper_axis_status
shaper_axis_status shaper_axis_status
#( #(
.DATA_WIDTH(READ_STATUS_WIDTH) .DATA_WIDTH(WRITE_STATUS_WIDTH)
) shaper_axis_status_write ) shaper_axis_status_write
( (
.clk(dma_clk), .clk(dma_clk),