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transferring tests

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This commit is contained in:
otroubi
2026-07-28 14:07:40 +03:00
parent ea9a6ad1e6
commit bec1cee7a8
3 changed files with 43 additions and 32 deletions
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rtl/accum/tests/Makefile
+11 -7
View File
@@ -13,20 +13,24 @@ FPGA_ARCH = artix7
RTL_DIR = ../src
# Simulation settings
SIM_TOP = tb_accumulator_top
SIM_RUNTIME ?= 10000 us
include ../../../scripts/vivado.mk
# Design sources only
SYN_FILES += $(filter-out %_tb.sv,$(sort $(shell find $(RTL_DIR) -type f -name '*.v' -o -type f -name '*.sv')))
SYN_FILES += $(sort $(shell find ../src -type f \( -name '*.v' -o -name '*.sv' \)))
# Testbench sources. Vivado puts these into "sim_1", Questa compiles them into "work".
TB_FILES += out_axis_fifo_tb.sv
TB_FILES += accum_full_tb.sv
XCI_FILES = $(sort $(shell find ../src -type f -name '*.xci'))
XCI_FILES = $(sort $(shell find $(RTL_DIR) -type f -name '*.xci'))
XDC_FILES += ../../../constraints/ax7a035b.xdc
XDC_FILES += test_timing.xdc
SYN_FILES += out_axis_fifo_tb.sv
SYN_FILES += accum_full_tb.sv
SIM_TOP = tb_accumulator_top
include ../../../scripts/vivado.mk
include ../../../scripts/questa.mk
program: $(PROJECT).bit
echo "open_hw_manager" > program.tcl
rtl/accum/tests/accum_full_tb.sv
+26 -19
View File
@@ -5,7 +5,7 @@ module tb_accumulator_top;
localparam DATA_WIDTH = 12;
localparam ACCUM_WIDTH = 32;
localparam N_MAX = 4096;
localparam WINDOW_SIZE = 65;
localparam MAX_WINDOW_SIZE = 65;
localparam PACKET_SIZE = 1024;
localparam READ_BATCH_SIZE = (PACKET_SIZE*8)/ACCUM_WIDTH;
localparam MAX_WORDS = N_MAX;
@@ -20,6 +20,7 @@ module tb_accumulator_top;
logic start;
logic [31:0] smp_num;
logic [15:0] seq_num;
logic [31:0] window_size;
logic req_ready;
wire send_req;
@@ -50,7 +51,6 @@ module tb_accumulator_top;
.DATA_WIDTH(DATA_WIDTH),
.ACCUM_WIDTH(ACCUM_WIDTH),
.N_MAX(N_MAX),
.WINDOW_SIZE(WINDOW_SIZE),
.PACKET_SIZE(PACKET_SIZE)
) dut (
.clk_in(clk_in),
@@ -60,6 +60,7 @@ module tb_accumulator_top;
.start(start),
.smp_num(smp_num),
.seq_num(seq_num),
.window_size(window_size),
.eth_clk_in(eth_clk_in),
.req_ready(req_ready),
.send_req(send_req),
@@ -104,6 +105,7 @@ module tb_accumulator_top;
s_axis_tvalid = 1'b0;
smp_num = '0;
seq_num = '0;
window_size = 32'd1;
req_ready = 1'b0;
m_axis_tready = 1'b1;
clear_scoreboard();
@@ -141,13 +143,14 @@ module tb_accumulator_top;
task automatic run_test(
input integer test_id,
input integer window_size_i,
input integer seq_num_i,
input integer smp_num_i,
input bit randomize_data,
input integer base_value,
input string test_name
);
logic [DATA_WIDTH-1:0] sample_mem [0:MAX_SEQ_NUM-1][0:(N_MAX*WINDOW_SIZE)-1];
logic [DATA_WIDTH-1:0] sample_mem [0:MAX_SEQ_NUM-1][0:(N_MAX*MAX_WINDOW_SIZE)-1];
integer seq_idx;
integer sample_idx;
integer word_idx;
@@ -165,22 +168,25 @@ module tb_accumulator_top;
tests_total = tests_total + 1;
errors_before = total_errors;
if (smp_num_i <= 0 || smp_num_i > N_MAX * WINDOW_SIZE || (smp_num_i % WINDOW_SIZE) != 0)
$fatal(1, "[%0s] invalid smp_num=%0d", test_name, smp_num_i);
if (window_size_i <= 0 || window_size_i > MAX_WINDOW_SIZE)
$fatal(1, "[%0s] invalid window_size=%0d", test_name, window_size_i);
if (smp_num_i <= 0 || smp_num_i > N_MAX * window_size_i || (smp_num_i % window_size_i) != 0)
$fatal(1, "[%0s] invalid smp_num=%0d for window_size=%0d", test_name, smp_num_i, window_size_i);
if (seq_num_i <= 0 || seq_num_i > MAX_SEQ_NUM)
$fatal(1, "[%0s] invalid seq_num=%0d", test_name, seq_num_i);
$display("\n========================================");
$display("TEST %0d: %0s", test_id, test_name);
$display("seq_num=%0d smp_num=%0d randomize=%0d", seq_num_i, smp_num_i, randomize_data);
$display("window_size=%0d seq_num=%0d smp_num=%0d randomize=%0d", window_size_i, seq_num_i, smp_num_i, randomize_data);
$display("========================================");
reset_dut();
smp_num = smp_num_i;
seq_num = seq_num_i;
window_size = window_size_i;
req_ready = 1'b1; // приемник готов заранее
exp_word_count = smp_num_i / WINDOW_SIZE;
exp_word_count = smp_num_i / window_size_i;
exp_packet_count = (exp_word_count + READ_BATCH_SIZE - 1) / READ_BATCH_SIZE;
for (seq_idx = 0; seq_idx < seq_num_i; seq_idx = seq_idx + 1) begin
@@ -196,8 +202,8 @@ module tb_accumulator_top;
for (word_idx = 0; word_idx < exp_word_count; word_idx = word_idx + 1) begin
local_sum = 0;
for (seq_idx = 0; seq_idx < seq_num_i; seq_idx = seq_idx + 1) begin
for (k = 0; k < WINDOW_SIZE; k = k + 1)
local_sum = local_sum + sample_mem[seq_idx][word_idx * WINDOW_SIZE + k];
for (k = 0; k < window_size_i; k = k + 1)
local_sum = local_sum + sample_mem[seq_idx][word_idx * window_size_i + k];
end
expected_words[word_idx] = local_sum[ACCUM_WIDTH-1:0];
$display(" expected[%0d] = %0d (0x%08x)", word_idx, expected_words[word_idx], expected_words[word_idx]);
@@ -318,16 +324,17 @@ module tb_accumulator_top;
reset_dut();
run_test(1, 1, 1 * WINDOW_SIZE, 1'b0, 1, "deterministic_small");
// $finish;
run_test(2, 2, 1 * WINDOW_SIZE, 1'b1, 0, "random_seq3_smp8");
run_test(3, 1, 16 * WINDOW_SIZE, 1'b1, 0, "random_seq5_smp16_multi_packet");
run_test(4, 2, 12 * WINDOW_SIZE, 1'b1, 0, "random_seq7_smp12");
run_test(5, 4, 256 * WINDOW_SIZE, 1'b1, 0, "random_max_smpnum");
run_test(6, 2, 1500 * WINDOW_SIZE, 1'b1, 0, "random_max_smpnum2");
run_test(7, 20, 1 * WINDOW_SIZE, 1'b1, 0, "random_20seq");
run_test(8, 20, 3 * WINDOW_SIZE, 1'b1, 0, "random_20seqx3");
run_test(9, 200, 1 * WINDOW_SIZE, 1'b1, 0, "random_200seq");
run_test(1, 1, 1, 1 * 1, 1'b0, 1, "w1_deterministic_small");
run_test(2, 1, 2, 16 * 1, 1'b1, 0, "w1_random_seq2_smp16");
run_test(3, 2, 2, 16 * 2, 1'b1, 0, "w2_random_seq2_smp32");
run_test(4, 3, 1, 16 * 3, 1'b1, 0, "w3_random_seq1_smp48");
run_test(5, 4, 2, 12 * 4, 1'b1, 0, "w4_random_seq2_smp48");
run_test(6, 65, 4, 256 * 65, 1'b1, 0, "w65_random_seq4_smp16640");
run_test(7, 2, 20, 3 * 2, 1'b1, 0, "w2_random_20seqx3");
run_test(8, 65, 20, 3 * 65, 1'b1, 0, "w65_random_20seqx3");
run_test(9, 1, 200, 1 * 1, 1'b1, 0, "w1_random_200seq");
run_test(10, 2, 200, 2 * 1, 1'b1, 0, "w2_random_200seq");
run_test(11, 65, 200, 65 * 1, 1'b1, 0, "w1_random_200seq");
$display("\n========================================");
$display("ALL TESTS COMPLETED");