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rtl: dma descriptor and status transmitter logic

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otroubi
2026-07-07 17:33:53 +03:00
parent d71655885c
commit bafd084f0d
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rtl/controller/src/dma_controller.sv Normal file
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module dma_controller
#(
parameter AXI_ADDR_WIDTH = 16,
parameter LEN_WIDTH = 20,
parameter TAG_WIDTH = 8,
parameter AXIS_ID_WIDTH = 8,
parameter AXIS_DEST_WIDTH = 8,
parameter AXIS_USER_WIDTH = 1
)
(
input dma_clk,
input rst,
input send,
input [127:0] desc_read,
input [127:0] desc_write,
input [127:0] status_read,
input [127:0] status_write,
//descriptor read
output wire [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_addr,
output wire [LEN_WIDTH-1:0] s_axis_read_desc_len,
output wire [TAG_WIDTH-1:0] s_axis_read_desc_tag,
output wire [AXIS_ID_WIDTH-1:0] s_axis_read_desc_id,
output wire [AXIS_DEST_WIDTH-1:0] s_axis_read_desc_dest,
output wire [AXIS_USER_WIDTH-1:0] s_axis_read_desc_user,
output wire s_axis_read_desc_valid,
input wire s_axis_read_desc_ready,
// descriptor write
output wire [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_addr,
output wire [LEN_WIDTH-1:0] s_axis_write_desc_len,
output wire [TAG_WIDTH-1:0] s_axis_write_desc_tag,
output wire s_axis_write_desc_valid,
input wire s_axis_write_desc_ready,
// status read
input wire [TAG_WIDTH-1:0] m_axis_read_desc_status_tag,
input wire [3:0] m_axis_read_desc_status_error,
input wire m_axis_read_desc_status_valid,
// status write
input wire [LEN_WIDTH-1:0] m_axis_write_desc_status_len,
input wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag,
input wire [AXIS_ID_WIDTH-1:0] m_axis_write_desc_status_id,
input wire [AXIS_DEST_WIDTH-1:0] m_axis_write_desc_status_dest,
input wire [AXIS_USER_WIDTH-1:0] m_axis_write_desc_status_user,
input wire [3:0] m_axis_write_desc_status_error,
input wire m_axis_write_desc_status_valid
);
endmodule