fix: timing. New DAC-ADC line code

designs/adc_dac_synchoronizer/sync_top.sv

@@ -30,28 +30,46 @@ module sync_top
     //------------------------------------------------------------
     wire dac_done, dac_request, adc_done, adc_request;
     wire [DAC_DATA_WIDTH-1:0] dac_signal;
-    wire [ADC_DATA_WIDTH-1:0] internal_wire_singnal;
-    wire [ADC_DATA_WIDTH-1:0] adc_singnal;
+    wire [ADC_DATA_WIDTH-1:0] internal_wire_signal; 
+    wire [ADC_DATA_WIDTH-1:0] adc_signal;
+
+    // 1. Адаптация разрядности и «заземление» лишних бит
     generate
         if (ADC_DATA_WIDTH > DAC_DATA_WIDTH) begin : g_pad_zeros
-            assign internal_wire_singnal = { {(ADC_DATA_WIDTH - DAC_DATA_WIDTH){1'b0}}, dac_signal };
-        end 
-        else begin : g_truncate
-            assign internal_wire_singnal = dac_signal[ADC_DATA_WIDTH-1:0];
+            // АЦП шире ЦАП: добиваем нулями старшие биты
+            assign internal_wire_signal = { {(ADC_DATA_WIDTH - DAC_DATA_WIDTH){1'b0}}, dac_signal };
+        end
+        else if (ADC_DATA_WIDTH < DAC_DATA_WIDTH) begin : g_truncate
+            // ЦАП шире АЦП (например, 14 -> 12): забираем младшие биты
+            assign internal_wire_signal = dac_signal[DAC_DATA_WIDTH-1:DAC_DATA_WIDTH-ADC_DATA_WIDTH];
+            (* dont_touch = "true" *) wire dummy;
+            assign dummy = ^dac_signal;
+        end
+        else begin : g_match
+            // Разрядности равны
+            assign internal_wire_signal = dac_signal;
         end
     endgenerate
+
     generate
-        if (USE_DELAY_LINE) begin
+        if (USE_DELAY_LINE > 0) begin : g_delay_line
             localparam int DELAY_LENGTH = USE_DELAY_LINE;
-            logic [DELAY_LENGTH:0][ADC_DATA_WIDTH-1:0] signal_delay_line;
+            // Двумерный массив для линии задержки
+            logic [DELAY_LENGTH-1:0][ADC_DATA_WIDTH-1:0] signal_delay_line;
+            
             always_ff @(posedge clk_dac) begin
-                signal_delay_line[0] <= internal_wire_singnal;
-                for (int i = 0; i < DELAY_LENGTH; i++)
+                signal_delay_line[0] <= internal_wire_signal;
+                for (int i = 0; i < DELAY_LENGTH-1; i++) begin
                     signal_delay_line[i+1] <= signal_delay_line[i];
+                end
             end
-            assign adc_singnal = signal_delay_line[DELAY_LENGTH];
-        end else
-            assign adc_singnal = internal_wire_singnal;
+            
+            // ИСПРАВЛЕНО: читаем из последнего элемента массива
+            assign adc_signal = signal_delay_line[DELAY_LENGTH-1];
+        end 
+        else begin : g_no_delay
+            assign adc_signal = internal_wire_signal;
+        end
     endgenerate
 
     //------------------------------------------------------------
@@ -127,7 +145,7 @@ module sync_top
     ) sampler_inst (
         .clk_in(clk_adc),
         .rst(rst_adc),
-        .data_in(adc_singnal),
+        .data_in(adc_signal),
         .out_of_range(out_of_range),
         .smp_num(smp_num),
         .m_axis_tdata(m_axis_tdata),