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rtl: sampler synchronization work, not totally ready

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otroubi
2026-06-09 21:07:09 +03:00
parent d90167984a
commit b0e886893b
2 changed files with 185 additions and 109 deletions
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57
rtl/sampler/src/sampler.sv
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@ -1,7 +1,5 @@
`timescale 1ns / 1ps
module sampler
#(
parameter DATA_WIDTH = 12,
@ -14,16 +12,16 @@ module sampler
input [DATA_WIDTH-1:0] data_in,
input out_of_range,
input [31:0] smp_num,
input sample_req,
input done,
output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
output logic m_axis_tvalid,
output logic sample_done
output logic request
);
(* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted;
(* MARK_DEBUG="true" *) logic out_of_range_reg;
(* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num;
(* MARK_DEBUG="true" *) logic enable;
(* MARK_DEBUG="true" *) logic enable, enable_d;
generate
if (PROCESS_MODE) begin
@ -68,20 +66,22 @@ module sampler
buffer_ready <= 0;
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= '0;
sample_done <= 0;
enable <= 0;
request <= 0;
end
else begin
buffer_ready <= 0;
if (sample_done && !sample_req) begin
sample_done <= 1'b0;
end
if (!enable && sample_req && !sample_done) begin
enable <= 1;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end
if (enable) begin
enable_d <= enable;
if (!enable) begin
if (request && done) begin
enable <= 1;
request <= 0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end else begin
request <= 1;
end
end else begin
if (!out_of_range_reg) begin
if (cnt_smp_num != smp_num_reg) begin
buffer <= data_converted;
@ -90,8 +90,6 @@ module sampler
end
else begin
cnt_smp_num <= '0;
sample_done <= 1'b1;
buffer_ready <= 0;
buffer <= '0;
enable <= 0;
end
@ -108,21 +106,21 @@ module sampler
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= 0;
sample_done <= 0;
request <= 0;
end
else begin
buffer_ready <= 0;
if (sample_done && !sample_req) begin
sample_done <= 1'b0;
end
if (!enable && sample_req && !sample_done) begin
enable <= 1;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end
if (enable) begin
if (!enable) begin
if (!request) request <= 1;
if (request && done) begin
enable <= 1;
request <= 0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end
end else begin
if (!out_of_range_reg) begin
if (cnt_smp_num != smp_num_reg) begin
if (cnt_smp_num < smp_num_reg) begin
cnt_smp_num <= cnt_smp_num +1;
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
if (cnt == PACK_FACTOR-1) begin
@ -135,7 +133,6 @@ module sampler
end
end
else begin
sample_done <= 1'b1;
cnt_smp_num <= '0;
buffer_ready <= 0;
buffer <= '0;