wrapper and makefile for a complete reflectometer and DMA test

designs/full_new_reflectometer/tests/reflectometer_and_dma/Makefile

@@ -0,0 +1,75 @@
+TOPLEVEL_LANG = verilog
+SIM ?= verilator
+
+PWD := $(shell pwd)
+
+WRAP_DIR = $(PWD)/../src
+RTL_CTRL_DIR  = $(PWD)/../../controller_new/src
+RTL_ACCUM_DIR = $(PWD)/../../accum/src
+RTL_GENERATOR_DIR = $(PWD)/../../generator/src
+RTL_SAMPLER_DIR = $(PWD)/../../sampler/src
+RTL_ADC_DAC_MODELS_DIR = $(PWD)/../reflectometer_base
+LIBS_DIR = $(PWD)/../../../external/rtl_libs
+
+#axi primitives
+VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_pkg.sv
+VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_if.sv
+VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axis_if.sv
+VERILOG_SOURCES += $(LIBS_DIR)/axi/axi_reg/axi4l_reg_map.sv
+
+#dma primitives
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/dma_reg_pkg.sv
+VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_rd.v
+VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_wr.v
+VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma.v
+VERILOG_SOURCES += $(WRAP_DIR)/axi_dma_wrapper_if.sv
+
+# controller primitives
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/controller.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/dma_controller.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/shaper_axis_desc.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/shaper_axis_status.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/controller_wrapper_axil.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/axi4l_reg_map_controller_pkg.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/axis_defaults_helper.sv
+VERILOG_SOURCES += $(RTL_CTRL_DIR)/axi4l_reg_map_controller.sv
+
+# accumulator primitives
+VERILOG_SOURCES += $(RTL_ACCUM_DIR)/adder.sv
+VERILOG_SOURCES += $(RTL_ACCUM_DIR)/accum.sv
+VERILOG_SOURCES += $(RTL_ACCUM_DIR)/out_axis_fifo.sv
+VERILOG_SOURCES += $(RTL_ACCUM_DIR)/accum_top.sv
+
+# generator primitives
+VERILOG_SOURCES += $(RTL_GENERATOR_DIR)/generator.sv
+
+#sampler_primitives
+VERILOG_SOURCES += $(RTL_SAMPLER_DIR)/sampler.sv
+
+# project primitives
+VERILOG_SOURCES += $(WRAP_DIR)/reflectometer_ip.sv
+VERILOG_SOURCES += $(WRAP_DIR)/reflectometer_and_dma_wrapper.sv
+
+# testbench primitives
+VERILOG_SOURCES += $(RTL_ADC_DAC_MODELS_DIR)/adc_model.sv
+VERILOG_SOURCES += $(RTL_ADC_DAC_MODELS_DIR)/dac_model.sv
+VERILOG_SOURCES += $(PWD)/tb_reflectometer_and_dma_wrapper.sv
+
+TOPLEVEL = tb_reflectometer_and_dma_wrapper
+MODULE = test_reflectometer_and_dma
+
+
+ifeq ($(SIM),verilator)
+    EXTRA_ARGS += --trace --trace-structs
+    EXTRA_ARGS += -I$(LIBS_DIR)/axi/rtl/
+    COMPILE_ARGS += -Wno-fatal
+    COMPILE_ARGS += -I$(LIBS_DIR)/axi/rtl/
+    EXTRA_ARGS += --trace
+    EXTRA_ARGS += --trace-structs
+    EXTRA_ARGS += --public-flat-rw
+    EXTRA_ARGS += -Wno-fatal
+    EXTRA_ARGS += --timing
+endif
+
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

designs/full_new_reflectometer/tests/reflectometer_and_dma/tb_reflectometer_and_dma_wrapper.sv

@@ -0,0 +1,282 @@
+import dma_reg_pkg::*;
+`timescale 1 ns / 1 ns
+
+module tb_reflectometer_and_dma_wrapper 
+#(
+        // parameters for base reflectometer works
+    parameter int unsigned DAC_DATA_WIDTH = 14,
+    parameter int unsigned ADC_DATA_WIDTH = 12,
+    parameter int unsigned PACK_FACTOR = 1,
+    parameter int unsigned PROCESS_MODE = 0,
+    parameter int unsigned ZERO_LEVEL = 8192,
+    parameter int unsigned ACCUM_WIDTH = 32,
+    parameter int unsigned N_MAX = 4096,
+    parameter int unsigned PACKET_SIZE = 1024,
+    parameter int unsigned RD_FIFO_WIDTH = 32,
+
+    // parameters for DMA and interfaces
+    parameter int unsigned ADDR_W             = 16,
+    parameter int unsigned DATA_W             = 32,
+    parameter int unsigned USER_W             = 1,
+
+    parameter int unsigned DAC_DATA_WIDTH     = 12,
+
+    parameter int unsigned AXI_DATA_WIDTH     = 32,
+
+    parameter int unsigned AXI_STRB_WIDTH     = AXI_DATA_WIDTH / 8,
+    parameter int unsigned AXI_ID_WIDTH       = 8,
+    parameter int unsigned AXI_USER_WIDTH     = 1,
+    parameter int unsigned AXI_MAX_BURST_LEN  = 16,
+
+    parameter int unsigned AXIS_DATA_WIDTH    = AXI_DATA_WIDTH,
+    parameter int unsigned AXIS_KEEP_ENABLE   = AXIS_DATA_WIDTH > 8,
+    parameter int unsigned AXIS_KEEP_WIDTH    = AXIS_DATA_WIDTH / 8,
+    parameter int unsigned AXIS_LAST_ENABLE   = 1,
+    parameter int unsigned AXIS_ID_ENABLE     = 1,
+    parameter int unsigned AXIS_DEST_ENABLE   = 0,
+    parameter int unsigned AXIS_USER_ENABLE   = 1,
+
+    parameter int unsigned ENABLE_SG          = 0,
+    parameter int unsigned ENABLE_UNALIGNED   = 0,
+
+    parameter int unsigned PIPELINE_OUTPUT    = 0
+)
+(
+    input  logic                       ctrl_clk,
+    input  logic                       rst_n,
+    output  wire                       locked,
+
+    input  logic [ADDR_W-1:0]   s_axil_awaddr,
+    input  logic [2:0]          s_axil_awprot,
+    input  logic                s_axil_awvalid,
+    output logic                s_axil_awready,
+
+    input  logic [DATA_W-1:0]   s_axil_wdata,
+    input  logic [DATA_W/8-1:0] s_axil_wstrb,
+    input  logic                s_axil_wvalid,
+    output logic                s_axil_wready,
+
+    output logic [1:0]          s_axil_bresp,
+    output logic                s_axil_bvalid,
+    input  logic                s_axil_bready,
+
+    input  logic [ADDR_W-1:0]   s_axil_araddr,
+    input  logic [2:0]          s_axil_arprot,
+    input  logic                s_axil_arvalid,
+    output logic                s_axil_arready,
+
+    output logic [DATA_W-1:0]   s_axil_rdata,
+    output logic [1:0]          s_axil_rresp,
+    output logic                s_axil_rvalid,
+    input  logic                s_axil_rready,
+
+    output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata,
+    output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep,
+    output wire                       m_axis_read_data_tvalid,
+    input  wire                       m_axis_read_data_tready,
+    output wire                       m_axis_read_data_tlast,
+    output wire [AXIS_ID_WIDTH-1:0]   m_axis_read_data_tid,
+    output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest,
+    output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser,
+
+     output wire [AXI_ID_WIDTH-1:0]   m_axi_awid,
+    output wire [AXI_ADDR_WIDTH-1:0]  m_axi_awaddr,
+    output wire [7:0]                 m_axi_awlen,
+    output wire [2:0]                 m_axi_awsize,
+    output wire [1:0]                 m_axi_awburst,
+    output wire                       m_axi_awlock,
+    output wire [3:0]                 m_axi_awcache,
+    output wire [2:0]                 m_axi_awprot,
+    output wire                       m_axi_awvalid,
+    input  wire                       m_axi_awready,
+    output wire [AXI_DATA_WIDTH-1:0]  m_axi_wdata,
+    output wire [AXI_STRB_WIDTH-1:0]  m_axi_wstrb,
+    output wire                       m_axi_wlast,
+    output wire                       m_axi_wvalid,
+    input  wire                       m_axi_wready,
+    input  wire [AXI_ID_WIDTH-1:0]    m_axi_bid,
+    input  wire [1:0]                 m_axi_bresp,
+    input  wire                       m_axi_bvalid,
+    output wire                       m_axi_bready,
+    output wire [AXI_ID_WIDTH-1:0]    m_axi_arid,
+    output wire [AXI_ADDR_WIDTH-1:0]  m_axi_araddr,
+    output wire [7:0]                 m_axi_arlen,
+    output wire [2:0]                 m_axi_arsize,
+    output wire [1:0]                 m_axi_arburst,
+    output wire                       m_axi_arlock,
+    output wire [3:0]                 m_axi_arcache,
+    output wire [2:0]                 m_axi_arprot,
+    output wire                       m_axi_arvalid,
+    input  wire                       m_axi_arready,
+    input  wire [AXI_ID_WIDTH-1:0]    m_axi_rid,
+    input  wire [AXI_DATA_WIDTH-1:0]  m_axi_rdata,
+    input  wire [1:0]                 m_axi_rresp,
+    input  wire                       m_axi_rlast,
+    input  wire                       m_axi_rvalid,
+    output wire                       m_axi_rready
+
+);
+
+  logic rst_n;
+  assign rst_n = ~rst;
+
+    // ---------------------------------------------------------------------------
+    // AXI-Lite flat -> axi4l_if
+    // ---------------------------------------------------------------------------
+
+  axi4l_if #(
+    .ADDR_W(ADDR_W),
+    .DATA_W(DATA_W),
+    .USER_W(USER_W)
+  ) axil_bus (
+    .aclk(ctrl_clk),
+    .aresetn(rst_n)
+  );
+
+  axi4l_flat_to_if #(
+    .ADDR_W(ADDR_W),
+    .DATA_W(DATA_W),
+    .USER_W(USER_W)
+  ) u_axil_flat_to_if (
+    .s_axil_awaddr (s_axil_awaddr),
+    .s_axil_awprot (s_axil_awprot),
+    .s_axil_awvalid(s_axil_awvalid),
+    .s_axil_awready(s_axil_awready),
+
+    .s_axil_wdata  (s_axil_wdata),
+    .s_axil_wstrb  (s_axil_wstrb),
+    .s_axil_wvalid (s_axil_wvalid),
+    .s_axil_wready (s_axil_wready),
+
+    .s_axil_bresp  (s_axil_bresp),
+    .s_axil_bvalid (s_axil_bvalid),
+    .s_axil_bready (s_axil_bready),
+
+    .s_axil_araddr (s_axil_araddr),
+    .s_axil_arprot (s_axil_arprot),
+    .s_axil_arvalid(s_axil_arvalid),
+    .s_axil_arready(s_axil_arready),
+
+    .s_axil_rdata  (s_axil_rdata),
+    .s_axil_rresp  (s_axil_rresp),
+    .s_axil_rvalid (s_axil_rvalid),
+    .s_axil_rready (s_axil_rready),
+
+    .m_axil(axil_bus)
+  );
+
+  // ---------------------------------------------------------------------------
+  // AXIS interfaces for the updated controller_wrapper_axil
+  // ---------------------------------------------------------------------------
+
+// AXIS READ DATA DMA MASTER output
+  axis_if #(
+    .DATA_W (AXIS_DATA_WIDTH),
+    .KEEP_W (AXIS_KEEP_WIDTH),
+    .ID_W   (AXIS_ID_WIDTH),
+    .DEST_W (AXIS_DEST_WIDTH),
+    .USER_W (AXIS_USER_WIDTH)
+  ) read_data (
+    .aclk(ctrl_clk),
+    .aresetn(rst_n)
+  );
+
+logic [AXIS_KEEP_WIDTH-1:0] unused_read_tstrb;
+
+axis_if_to_flat #(
+    .DATA_W (AXIS_DATA_WIDTH),
+    .KEEP_W (AXIS_KEEP_WIDTH),
+    .ID_W   (AXIS_ID_WIDTH),
+    .DEST_W (AXIS_DEST_WIDTH),
+    .USER_W (AXIS_USER_WIDTH)
+) u_read_data_if_to_flat (
+    .s_axis(read_data),
+
+    .m_axis_tdata (m_axis_read_data_tdata),
+    .m_axis_tkeep (m_axis_read_data_tkeep),
+    .m_axis_tstrb (unused_read_tstrb),
+    .m_axis_tlast (m_axis_read_data_tlast),
+    .m_axis_tid   (m_axis_read_data_tid),
+    .m_axis_tdest (m_axis_read_data_tdest),
+    .m_axis_tuser (m_axis_read_data_tuser),
+    .m_axis_tvalid(m_axis_read_data_tvalid),
+    .m_axis_tready(m_axis_read_data_tready)
+);
+
+    // Интерфейс хендшейка с MAC-PHY
+    wire  send_request;
+    logic request_ready;
+    // Сигнал между ЦАП и АЦП
+    real signal_voltage;
+
+ // ADC интерфейс
+    wire                       clk_adc;
+    wire                       adc_otr;
+    wire [ADC_DATA_WIDTH-1:0]  adc_data;
+
+       virtual_adc_model #( // default voltage range is +/- 5V
+        .ADC_DATA_WIDTH(ADC_DATA_WIDTH)
+    ) virtual_adc (
+        .clk_i(clk_adc),
+        .voltage_i(signal_voltage),
+        .otr_o(adc_otr),
+        .data_o(adc_data)
+    );
+
+     // DAC интерфейс
+    wire                       clk_dac;
+    wire                       dac_wrt;
+    wire [DAC_DATA_WIDTH-1:0]  dac_data;
+
+    virtual_dac_model #( // default voltage range is +/- 5V
+        .DAC_DATA_WIDTH(DAC_DATA_WIDTH)
+        // ,.VOLTAGE_GAIN(2)
+    ) virtual_dac (
+        .clk_i(clk_dac),
+        .wrt_i(dac_wrt),
+        .data_i(dac_data),
+        .voltage_o(signal_voltage)
+    );
+
+    reflectometer_and_dma_wrapper #(
+        .DAC_DATA_WIDTH(DAC_DATA_WIDTH),
+        .ADC_DATA_WIDTH(ADC_DATA_WIDTH),
+        .ADC_DATA_WIDTH(ADC_DATA_WIDTH),
+        .PACK_FACTOR(PACK_FACTOR),
+        .PROCESS_MODE(PROCESS_MODE),
+        .ZERO_LEVEL(ZERO_LEVEL),
+        .ACCUM_WIDTH(ACCUM_WIDTH),
+        .N_MAX(N_MAX),
+        .PACKET_SIZE(PACKET_SIZE),
+        .RD_FIFO_WIDTH(RD_FIFO_WIDTH),
+
+        .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
+        .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
+        .AXI_USER_WIDTH(AXI_USER_WIDTH),
+        .AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
+        .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
+        .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
+        .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
+        .AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
+        .AXIS_ID_ENABLE(AXIS_ID_ENABLE),
+        .AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
+        .AXIS_USER_ENABLE(AXIS_USER_ENABLE),
+        .ENABLE_SG(ENABLE_SG),
+        .ENABLE_UNALIGNED(ENABLE_UNALIGNED)
+    ) reflectometer_and_dma_wrapper_dut (
+        .ctrl_clk(ctrl_clk),
+        .rst_n(rst_n),
+        .locked(locked),
+        .s_axil(axil_bus),
+        .m_axi(m_axi),
+        .m_axis_read_data(read_data),
+
+        .dac_clk_o(clk_dac),
+        .dac_data(dac_data),
+        .dac_wrt(dac_wrt),
+        .adc_clk_o(clk_adc),
+        .adc_data(adc_data),
+        .adc_otr(adc_otr)
+    );
+
+endmodule

designs/full_new_reflectometer/tests/reflectometer_and_dma/test_timing.xdc

@@ -0,0 +1,7 @@
+# Primary clocks
+create_clock -name ref_clock    -period 5.000  [get_ports ctrl_clk]
+
+set clk_125_name [get_clocks -of_objects [get_pins generator_inst/clk_dac_125]]
+set clk_65_name  [get_clocks -of_objects [get_pins accumulator_top_inst/clk_adc_65]]
+
+set_clock_groups -asynchronous -group $clk_125_name -group $clk_65_name