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fix: patch for sampler

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upd: reflectometer TB readaout data task
This commit is contained in:
babintsev.lv
2026-07-17 17:29:58 +03:00
parent 04eb927a25
commit a528838741
2 changed files with 77 additions and 40 deletions
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102
designs/reflectometer_base/reflectometer_tb.sv
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@ -11,13 +11,13 @@ module reflectometer_tb;
localparam LOGIC_ZERO_LEVEL = 0; // DAC -5V for logic zero
localparam VOLTAGE_ZERO_LEVEL = 2**(DAC_DATA_WIDTH-1); // DAC 0V for logic zero
localparam PACK_FACTOR = 1; // not used in TB
localparam PROCESS_MODE = 0; // 0 - uint, 1 - int
localparam PROCESS_MODE = 1; // 0 - uint, 1 - int
localparam ACCUM_WIDTH = 32; // accumulator number bit witdth
localparam N_MAX = 4096; // max value of windows to average by experiments
localparam WINDOW_SIZE = 65; // fixed subwindow size to average by time
localparam PACKET_SIZE = 1024; // bytes per UDP packet
localparam ZERO_LEVEL = VOLTAGE_ZERO_LEVEL; // "logic" VS "true"
localparam ZERO_LEVEL = LOGIC_ZERO_LEVEL; // "logic" VS "voltage"
localparam CLK_ETH_PHY_PERIOD = 8.000; // 125 MHz
localparam CLK_REF_PERIOD = 5.000; // 200 MHz
@ -63,7 +63,7 @@ module reflectometer_tb;
wire [ADC_DATA_WIDTH-1:0] adc_data;
// Интерфейс хендшейка с MAC-PHY
wire send_request;
logic request_ready = 1'b0;
logic request_ready;
// Сигналы ЦАП и АЦП
real signal_voltage;
@ -72,6 +72,7 @@ module reflectometer_tb;
//------------------------------------------------------------
virtual_dac_model #( // default voltage range is +/- 5V
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
// ,.VOLTAGE_GAIN(2)
) virtual_dac (
.clk_i(clk_dac),
.wrt_i(dac_wrt),
@ -149,6 +150,7 @@ module reflectometer_tb;
//------------------------------------------------------------
// Таски для тестирования
//------------------------------------------------------------
// Таски работы с AXI-Stream
task automatic dut_soft_reset(virtual axis_if#(8).tb vif);
logic [7:0] tx_packet[];
tx_packet = '{8'h0f};
@ -160,6 +162,7 @@ module reflectometer_tb;
tx_packet = '{8'hf0};
vif.master_send(tx_packet);
endtask
task automatic dut_send_system_config(
virtual axis_if#(8).tb vif,
input logic [31:0] pulse_width,
@ -183,19 +186,63 @@ module reflectometer_tb;
endtask
// Таски сбора и обработки статистики
task automatic dut_read_output(
virtual axis_if#(8).tb vif,
input int sample_num,
input bit randomize_recv_delays,
output int output_data[]
);
logic [7:0] rx_packet[];
logic [ACCUM_WIDTH-1:0] data_packet[];
int packet_num = $ceil(real'(sample_num / WINDOW_SIZE) / real'(PACKET_SIZE));
int numbers_per_packet = PACKET_SIZE/(ACCUM_WIDTH/8);
int idx = 0;
if (sample_num % WINDOW_SIZE) begin
$display("[TB] -dut_read_output- Error, sample_num must be multiple of WINDOW_SIZE: %0d %% %0d = %0d", sample_num, WINDOW_SIZE, sample_num % WINDOW_SIZE);
$finish;
end
data_packet = new[numbers_per_packet];
output_data = new[numbers_per_packet * packet_num];
// count send_request posedge todo
// timeout todo
// recv loop
for (int i = 0; i < packet_num; i++) begin
// randomize_recv_delays todo
request_ready = 1;
vif.slave_recv(rx_packet);
request_ready = 0;
// unpack values
data_packet = {<< byte {rx_packet}};
data_packet = {<< ACCUM_WIDTH {data_packet}};
// copy and convert values
for (int j = 0; j < data_packet.size(); j++) begin
output_data[i * data_packet.size() + j] = int'(data_packet[j]);
end
end
// wait for dut.finish posedge todo
// timeout todo
// error handling todo
endtask
//------------------------------------------------------------
// ОСНОВНОЙ ПРОЦЕСС ТЕСТИРОВАНИЯ
//------------------------------------------------------------
initial begin
logic [7:0] rx_packet[];
int output_data[];
automatic virtual axis_if.tb control_vif = axis_control_if.tb;
automatic virtual axis_if.tb accumulator_vif = axis_accumulator_if.tb;
$display("[TB] Tests start");
$display("[TB] DUT initializaton");
// Инициализация
request_ready = 0;
rst_n = 0;
#100;
rst_n = 1;
@ -205,38 +252,33 @@ module reflectometer_tb;
dut_soft_reset(control_vif);
#100;
// Тесты
$display("[TB] Tests start");
dut_send_system_config(
.vif(control_vif),
.pulse_width(32'd12345),
.pulse_period(32'd50000),
.pulse_num(16'd10),
.pulse_height(14'd16000), // 0V
.pulse_period_adc(32'd26000)
.pulse_width(32'd123),
.pulse_period(32'd5000),
.pulse_num(16'd1),
.pulse_height(14'd15000), // 0V
.pulse_period_adc(32'd2600)
);
#100;
dut_start(control_vif);
#1000;
request_ready = 1'b1;
accumulator_vif.slave_recv(rx_packet);
$display("receive %0d bytes", rx_packet.size());
for (int i = 0; i < rx_packet.size(); i+=4) begin
$write("%0d ", {rx_packet[i], rx_packet[i+1], rx_packet[i+2], rx_packet[i+3]});
dut_read_output(
.vif(accumulator_vif),
.sample_num(2600),
.randomize_recv_delays(0),
.output_data(output_data)
);
$display("Received %0d numbers", output_data.size());
for (int i = 0; i < output_data.size(); i++) begin
$write("%0d ", output_data[i]);
end
$display("");
#1000;
request_ready = 1'b1;
accumulator_vif.slave_recv(rx_packet);
$display("receive %0d bytes", rx_packet.size());
for (int i = 0; i < rx_packet.size(); i+=4) begin
$write("%0d ", {rx_packet[i], rx_packet[i+1], rx_packet[i+2], rx_packet[i+3]});
end
$display("");
// wait();
// #100000;
// #93000;
// rst_n = 0;
#10000
$display("[TB] ALL PASSED");
$finish;
end

11
rtl/sampler/src/sampler.sv
View File

@ -27,18 +27,13 @@ module sampler
data_converted = '0;
if (PROCESS_MODE) begin
if (out_of_range) begin
if (data_in[DATA_WIDTH-1]==1'b1) data_converted = {1'b1, {(DATA_WIDTH-2){1'b0}}};
else if (data_in[DATA_WIDTH-1]==1'b0) data_converted = {1'b0, {(DATA_WIDTH-2){1'b1}}};
data_converted = {~data_in[DATA_WIDTH-1], {(DATA_WIDTH-1){data_in[DATA_WIDTH-1]}}};
end else begin
if (data_in == {1'b1, {(DATA_WIDTH-1){1'b0}}})
data_converted = data_in;
else
data_converted = data_in[DATA_WIDTH-1] ?{1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)}:data_in;
data_converted = {~data_in[DATA_WIDTH-1], data_in[DATA_WIDTH-2:0]};
end
end else begin
if (out_of_range) begin
if (data_in[DATA_WIDTH-1]==1'b1) data_converted = '1;
else if (data_in[DATA_WIDTH-1]==1'b0) data_converted = '0;
data_converted = {DATA_WIDTH{data_in[DATA_WIDTH-1]}};
end else begin
data_converted = data_in;
end