From 9fd311d6714999331cf7aed355db5d92a36a80e8 Mon Sep 17 00:00:00 2001 From: Phil Date: Thu, 30 Apr 2026 13:05:33 +0300 Subject: [PATCH] chore: add debug XDC for main project --- designs/reflectometer/debug.xdc | 151 ++++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/designs/reflectometer/debug.xdc b/designs/reflectometer/debug.xdc index 430dc92..8307e09 100644 --- a/designs/reflectometer/debug.xdc +++ b/designs/reflectometer/debug.xdc @@ -1,2 +1,153 @@ set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst] + +create_debug_core u_ila_0 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property port_width 1 [get_debug_ports u_ila_0/clk] +connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +set_property port_width 16 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {accumulator_top_dut/accum_main/adder_dut/cnt[0]} {accumulator_top_dut/accum_main/adder_dut/cnt[1]} {accumulator_top_dut/accum_main/adder_dut/cnt[2]} {accumulator_top_dut/accum_main/adder_dut/cnt[3]} {accumulator_top_dut/accum_main/adder_dut/cnt[4]} {accumulator_top_dut/accum_main/adder_dut/cnt[5]} {accumulator_top_dut/accum_main/adder_dut/cnt[6]} {accumulator_top_dut/accum_main/adder_dut/cnt[7]} {accumulator_top_dut/accum_main/adder_dut/cnt[8]} {accumulator_top_dut/accum_main/adder_dut/cnt[9]} {accumulator_top_dut/accum_main/adder_dut/cnt[10]} {accumulator_top_dut/accum_main/adder_dut/cnt[11]} {accumulator_top_dut/accum_main/adder_dut/cnt[12]} {accumulator_top_dut/accum_main/adder_dut/cnt[13]} {accumulator_top_dut/accum_main/adder_dut/cnt[14]} {accumulator_top_dut/accum_main/adder_dut/cnt[15]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +set_property port_width 4 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {accumulator_top_dut/accum_main/wr_state[0]} {accumulator_top_dut/accum_main/wr_state[1]} {accumulator_top_dut/accum_main/wr_state[2]} {accumulator_top_dut/accum_main/wr_state[3]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +set_property port_width 3 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {accumulator_top_dut/output_async_fifo/wr_state[0]} {accumulator_top_dut/output_async_fifo/wr_state[1]} {accumulator_top_dut/output_async_fifo/wr_state[2]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +set_property port_width 32 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {adc_pulse_period[0]} {adc_pulse_period[1]} {adc_pulse_period[2]} {adc_pulse_period[3]} {adc_pulse_period[4]} {adc_pulse_period[5]} {adc_pulse_period[6]} {adc_pulse_period[7]} {adc_pulse_period[8]} {adc_pulse_period[9]} {adc_pulse_period[10]} {adc_pulse_period[11]} {adc_pulse_period[12]} {adc_pulse_period[13]} {adc_pulse_period[14]} {adc_pulse_period[15]} {adc_pulse_period[16]} {adc_pulse_period[17]} {adc_pulse_period[18]} {adc_pulse_period[19]} {adc_pulse_period[20]} {adc_pulse_period[21]} {adc_pulse_period[22]} {adc_pulse_period[23]} {adc_pulse_period[24]} {adc_pulse_period[25]} {adc_pulse_period[26]} {adc_pulse_period[27]} {adc_pulse_period[28]} {adc_pulse_period[29]} {adc_pulse_period[30]} {adc_pulse_period[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +set_property port_width 12 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {ch2_data_IBUF[0]} {ch2_data_IBUF[1]} {ch2_data_IBUF[2]} {ch2_data_IBUF[3]} {ch2_data_IBUF[4]} {ch2_data_IBUF[5]} {ch2_data_IBUF[6]} {ch2_data_IBUF[7]} {ch2_data_IBUF[8]} {ch2_data_IBUF[9]} {ch2_data_IBUF[10]} {ch2_data_IBUF[11]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +set_property port_width 16 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {adc_pulse_num[0]} {adc_pulse_num[1]} {adc_pulse_num[2]} {adc_pulse_num[3]} {adc_pulse_num[4]} {adc_pulse_num[5]} {adc_pulse_num[6]} {adc_pulse_num[7]} {adc_pulse_num[8]} {adc_pulse_num[9]} {adc_pulse_num[10]} {adc_pulse_num[11]} {adc_pulse_num[12]} {adc_pulse_num[13]} {adc_pulse_num[14]} {adc_pulse_num[15]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +set_property port_width 12 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {accum_m_axis_tdata[0]} {accum_m_axis_tdata[1]} {accum_m_axis_tdata[2]} {accum_m_axis_tdata[3]} {accum_m_axis_tdata[4]} {accum_m_axis_tdata[5]} {accum_m_axis_tdata[6]} {accum_m_axis_tdata[7]} {accum_m_axis_tdata[8]} {accum_m_axis_tdata[9]} {accum_m_axis_tdata[10]} {accum_m_axis_tdata[11]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +set_property port_width 1 [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list acum_m_axis_tvalid]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +set_property port_width 1 [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list adc_rst]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +set_property port_width 1 [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list adc_start]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +set_property port_width 1 [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list finish]] +create_debug_core u_ila_1 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1] +set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_1] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1] +set_property port_width 1 [get_debug_ports u_ila_1/clk] +connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0] +set_property port_width 14 [get_debug_ports u_ila_1/probe0] +connect_debug_port u_ila_1/probe0 [get_nets [list {dac_pulse_height[0]} {dac_pulse_height[1]} {dac_pulse_height[2]} {dac_pulse_height[3]} {dac_pulse_height[4]} {dac_pulse_height[5]} {dac_pulse_height[6]} {dac_pulse_height[7]} {dac_pulse_height[8]} {dac_pulse_height[9]} {dac_pulse_height[10]} {dac_pulse_height[11]} {dac_pulse_height[12]} {dac_pulse_height[13]}]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1] +set_property port_width 1 [get_debug_ports u_ila_1/probe1] +connect_debug_port u_ila_1/probe1 [get_nets [list dac_rst]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2] +set_property port_width 1 [get_debug_ports u_ila_1/probe2] +connect_debug_port u_ila_1/probe2 [get_nets [list dac_start]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3] +set_property port_width 1 [get_debug_ports u_ila_1/probe3] +connect_debug_port u_ila_1/probe3 [get_nets [list debug_dac_OBUF]] +create_debug_core u_ila_2 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2] +set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_2] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2] +set_property port_width 1 [get_debug_ports u_ila_2/clk] +connect_debug_port u_ila_2/clk [get_nets [list rgmii_rxc_IBUF_BUFG]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0] +set_property port_width 3 [get_debug_ports u_ila_2/probe0] +connect_debug_port u_ila_2/probe0 [get_nets [list {accumulator_top_dut/output_async_fifo/rd_state[0]} {accumulator_top_dut/output_async_fifo/rd_state[1]} {accumulator_top_dut/output_async_fifo/rd_state[2]}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1] +set_property port_width 8 [get_debug_ports u_ila_2/probe1] +connect_debug_port u_ila_2/probe1 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2] +set_property port_width 8 [get_debug_ports u_ila_2/probe2] +connect_debug_port u_ila_2/probe2 [get_nets [list {s_axis_tx_tdata[0]} {s_axis_tx_tdata[1]} {s_axis_tx_tdata[2]} {s_axis_tx_tdata[3]} {s_axis_tx_tdata[4]} {s_axis_tx_tdata[5]} {s_axis_tx_tdata[6]} {s_axis_tx_tdata[7]}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3] +set_property port_width 3 [get_debug_ports u_ila_2/probe3] +connect_debug_port u_ila_2/probe3 [get_nets [list {udp_ctrl_inst/eth_state[0]} {udp_ctrl_inst/eth_state[1]} {udp_ctrl_inst/eth_state[2]}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4] +set_property port_width 1 [get_debug_ports u_ila_2/probe4] +connect_debug_port u_ila_2/probe4 [get_nets [list udp_ctrl_inst/axis_hs]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5] +set_property port_width 1 [get_debug_ports u_ila_2/probe5] +connect_debug_port u_ila_2/probe5 [get_nets [list udp_ctrl_inst/busy_flag_eth]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe6] +set_property port_width 1 [get_debug_ports u_ila_2/probe6] +connect_debug_port u_ila_2/probe6 [get_nets [list m_axis_rx_tlast]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe7] +set_property port_width 1 [get_debug_ports u_ila_2/probe7] +connect_debug_port u_ila_2/probe7 [get_nets [list m_axis_rx_tready]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe8] +set_property port_width 1 [get_debug_ports u_ila_2/probe8] +connect_debug_port u_ila_2/probe8 [get_nets [list m_axis_rx_tvalid]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe9] +set_property port_width 1 [get_debug_ports u_ila_2/probe9] +connect_debug_port u_ila_2/probe9 [get_nets [list req_ready]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe10] +set_property port_width 1 [get_debug_ports u_ila_2/probe10] +connect_debug_port u_ila_2/probe10 [get_nets [list s_axis_tx_tlast]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe11] +set_property port_width 1 [get_debug_ports u_ila_2/probe11] +connect_debug_port u_ila_2/probe11 [get_nets [list s_axis_tx_tready]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe12] +set_property port_width 1 [get_debug_ports u_ila_2/probe12] +connect_debug_port u_ila_2/probe12 [get_nets [list s_axis_tx_tvalid]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe13] +set_property port_width 1 [get_debug_ports u_ila_2/probe13] +connect_debug_port u_ila_2/probe13 [get_nets [list send_req]] +set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] +set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] +set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] +connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]