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debugging controller

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This commit is contained in:
otroubi
2026-07-08 17:53:25 +03:00
parent e7c45101d1
commit 99a344d534
4 changed files with 397 additions and 381 deletions
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69
rtl/controller/src/controller.sv
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@ -10,9 +10,13 @@ module control #(
// adc_clk_in domain
input logic finish,
input logic [127:0] cfg_bus,
input logic [127:0] cfg_bus_input,
input logic cfg_bus_valid,
input logic start,
// status signals
output logic busy,
// dac_clk_in domain outputs
output logic [31:0] dac_pulse_width,
output logic [31:0] dac_pulse_period,
@ -83,6 +87,10 @@ module control #(
assign dac_rst_int = dac_rst_ff2;
assign adc_rst_int = adc_rst_ff2;
// Pending ACKs for config delivery
logic cfg_wait_dac_ack;
logic cfg_wait_adc_ack;
wire cfg_busy = cfg_wait_dac_ack || cfg_wait_adc_ack;
// Event toggles cntrl -> DAC/ADC
logic start_toggle;
@ -99,8 +107,8 @@ module control #(
(* ASYNC_REG = "TRUE" *) logic cfg_ack_toggle_dac_meta, cfg_ack_toggle_dac_sync, cfg_ack_toggle_dac_sync_d;
(* ASYNC_REG = "TRUE" *) logic cfg_ack_toggle_adc_meta, cfg_ack_toggle_adc_sync, cfg_ack_toggle_adc_sync_d;
wire cfg_ack_pulse_dac_eth = cfg_ack_toggle_dac_sync ^ cfg_ack_toggle_dac_sync_d;
wire cfg_ack_pulse_adc_eth = cfg_ack_toggle_adc_sync ^ cfg_ack_toggle_adc_sync_d;
wire cfg_ack_pulse_dac = cfg_ack_toggle_dac_sync ^ cfg_ack_toggle_dac_sync_d;
wire cfg_ack_pulse_adc = cfg_ack_toggle_adc_sync ^ cfg_ack_toggle_adc_sync_d;
always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin
if (ctrl_rst) begin
@ -148,7 +156,54 @@ module control #(
end
end
// ETH -> DAC: start/reset event sync
logic [127:0] cfg_bus;
always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin
if (ctrl_rst) begin
cfg_bus <= '0;
busy <= 0;
start_toggle <= 0;
rst_toggle <= 0;
cfg_req_toggle_dac <= 0;
cfg_req_toggle_adc <= 0;
cfg_wait_dac_ack <= 0;
cfg_wait_adc_ack <= 0;
end else begin
if (finish_pulse) begin
busy <= 0;
end
if (cfg_ack_pulse_dac) begin
cfg_wait_dac_ack <= 1'b0;
end
if (cfg_ack_pulse_adc) begin
cfg_wait_adc_ack <= 1'b0;
end
if (cfg_bus_valid && !busy && !cfg_busy) begin
cfg_bus <= cfg_bus_input;
cfg_req_toggle_dac <= ~cfg_req_toggle_dac;
cfg_req_toggle_adc <= ~cfg_req_toggle_adc;
cfg_wait_dac_ack <= 1;
cfg_wait_adc_ack <= 1;
end
if (start && !busy && !cfg_busy) begin
start_toggle <= ~start_toggle;
busy <= 1;
end
if (rst_soft) begin
rst_toggle <= ~rst_toggle;
end
end
end
// cntrl -> DAC: start/reset event sync
(* ASYNC_REG = "TRUE" *) logic start_meta_dac, start_sync_dac;
logic start_sync_dac_d;
(* ASYNC_REG = "TRUE" *) logic rst_meta_dac, rst_sync_dac;
@ -236,7 +291,7 @@ module control #(
dac_pulse_num <= '0;
dac_pulse_height <= '0;
end else begin
cfg_req_meta_dac <= cfg_req_toggle_dac_eth;
cfg_req_meta_dac <= cfg_req_toggle_dac;
cfg_req_sync_dac <= cfg_req_meta_dac;
cfg_req_sync_dac_d <= cfg_req_sync_dac;
@ -251,7 +306,7 @@ module control #(
end
end
// ETH -> ADC config CDC
// cntrl -> ADC config CDC
logic cfg_req_meta_adc, cfg_req_sync_adc, cfg_req_sync_adc_d;
wire cfg_req_pulse_adc = cfg_req_sync_adc ^ cfg_req_sync_adc_d;
@ -265,7 +320,7 @@ module control #(
adc_pulse_period <= '0;
adc_pulse_num <= '0;
end else begin
cfg_req_meta_adc <= cfg_req_toggle_adc_eth;
cfg_req_meta_adc <= cfg_req_toggle_adc;
cfg_req_sync_adc <= cfg_req_meta_adc;
cfg_req_sync_adc_d <= cfg_req_sync_adc;