strapping for the test

designs/controller_dma_connective/src/wrapper_controller_dma_accum.sv

@@ -1,6 +1,6 @@
 import dma_reg_pkg::*;
 
-module wrapper_controller_dma_accum
+module wrapper_controller_dma_accum 
 #(
     parameter int unsigned ADDR_W             = 16,
     parameter int unsigned DATA_W             = 32,
@@ -43,29 +43,26 @@ module wrapper_controller_dma_accum
 
     // adc_clk_in domain
 
-    input logic [AXI_DATA_WIDTH-1:0]   sampler_m_axis_tdata,
+    input logic [ADC_DATA_WIDTH-1:0]   sampler_m_axis_tdata,
     input logic                        sampler_m_axis_tvalid,
 
-    // dac_clk_in domain outputs
-    output logic [31:0]                dac_pulse_width,
-    output logic [31:0]                dac_pulse_period,
-    output logic [DAC_DATA_WIDTH-1:0]  dac_pulse_height,
-    output logic [15:0]                dac_pulse_num,
-
-    // adc_clk_in domain outputs
-    output logic [31:0]                adc_pulse_period,
-    output logic [15:0]                adc_pulse_num,
-
-    // pulse outputs
-    output logic                       dac_start,
-    output logic                       dac_rst
-
     axis_if.master    m_axis_read_data
 );
 
 logic workflow_done, processing_done;
 logic [31:0] window_size;
 logic adc_start, adc_rst;
+logic [31:0]                dac_pulse_width;
+logic [31:0]                dac_pulse_period;
+logic [DAC_DATA_WIDTH-1:0]  dac_pulse_height;
+logic [15:0]                dac_pulse_num;
+
+    // adc_clk_in domain outputs
+logic [31:0]                adc_pulse_period;
+logic [15:0]                adc_pulse_num;
+
+    // pulse outputs
+logic  dac_start, dac_rst;
 
 axis_if #(
     .DATA_W($bits(dma_read_status_t)),
@@ -218,7 +215,7 @@ accumulator_top #(
     ) accumulator_top_inst (
         .clk_in(clk_sampler),
         .rst(adc_rst),
-        .s_axis_tdata(sampler_m_axis_tdata[ADC_DATA_WIDTH-1:0]),
+        .s_axis_tdata(sampler_m_axis_tdata),
         .s_axis_tvalid(sampler_m_axis_tvalid),
         .start(adc_start),
         .smp_num(adc_pulse_period),

designs/controller_dma_connective/tests/dma_accum_connection/tb_controller_dma_accum_wrapper_axil.sv

@@ -33,6 +33,8 @@ module tb_controller_dma_accum_wrapper_axil #(
     parameter int unsigned RD_FIFO_WIDTH = 32
 )(
   input  logic                 ctrl_clk,
+  input  logic                 adc_clk_in,
+  input  logic                 dac_clk_in,
   input  logic                 rst,
 
   input  logic [ADDR_W-1:0]   s_axil_awaddr,
@@ -59,74 +61,22 @@ module tb_controller_dma_accum_wrapper_axil #(
   output logic                s_axil_rvalid,
   input  logic                s_axil_rready,
 
-  input  wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata,
-    input  wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep,
-    input  wire                       s_axis_write_data_tvalid,
-    output wire                       s_axis_write_data_tready,
-    input  wire                       s_axis_write_data_tlast,
-    input  wire [AXIS_ID_WIDTH-1:0]   s_axis_write_data_tid,
-    input  wire [AXIS_DEST_WIDTH-1:0] s_axis_write_data_tdest,
-    input  wire [AXIS_USER_WIDTH-1:0] s_axis_write_data_tuser,
-
     output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata,
     output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep,
     output wire                       m_axis_read_data_tvalid,
     input  wire                       m_axis_read_data_tready,
     output wire                       m_axis_read_data_tlast,
     output wire [AXIS_ID_WIDTH-1:0]   m_axis_read_data_tid,
-    output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest,
+    output wire [dma_reg_pkg::AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest,
-    output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser,
+    output wire [dma_reg_pkg::AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser,
 
-     output wire [AXI_ID_WIDTH-1:0]    m_axi_awid,
+    input wire [ADC_DATA_WIDTH-1:0]   sampler_m_axis_tdata,
-    output wire [AXI_ADDR_WIDTH-1:0]  m_axi_awaddr,
+    input wire                        sampler_m_axis_tvalid
-    output wire [7:0]                 m_axi_awlen,
-    output wire [2:0]                 m_axi_awsize,
-    output wire [1:0]                 m_axi_awburst,
-    output wire                       m_axi_awlock,
-    output wire [3:0]                 m_axi_awcache,
-    output wire [2:0]                 m_axi_awprot,
-    output wire                       m_axi_awvalid,
-    input  wire                       m_axi_awready,
-    output wire [AXI_DATA_WIDTH-1:0]  m_axi_wdata,
-    output wire [AXI_STRB_WIDTH-1:0]  m_axi_wstrb,
-    output wire                       m_axi_wlast,
-    output wire                       m_axi_wvalid,
-    input  wire                       m_axi_wready,
-    input  wire [AXI_ID_WIDTH-1:0]    m_axi_bid,
-    input  wire [1:0]                 m_axi_bresp,
-    input  wire                       m_axi_bvalid,
-    output wire                       m_axi_bready,
-    output wire [AXI_ID_WIDTH-1:0]    m_axi_arid,
-    output wire [AXI_ADDR_WIDTH-1:0]  m_axi_araddr,
-    output wire [7:0]                 m_axi_arlen,
-    output wire [2:0]                 m_axi_arsize,
-    output wire [1:0]                 m_axi_arburst,
-    output wire                       m_axi_arlock,
-    output wire [3:0]                 m_axi_arcache,
-    output wire [2:0]                 m_axi_arprot,
-    output wire                       m_axi_arvalid,
-    input  wire                       m_axi_arready,
-    input  wire [AXI_ID_WIDTH-1:0]    m_axi_rid,
-    input  wire [AXI_DATA_WIDTH-1:0]  m_axi_rdata,
-    input  wire [1:0]                 m_axi_rresp,
-    input  wire                       m_axi_rlast,
-    input  wire                       m_axi_rvalid,
-    output wire                       m_axi_rready
-
-    
 );
 
-  logic rst_n;
+logic rst_n;
-  assign rst_n = ~rst;
 
-  // Для минимального теста держим все clock domain-ы на одном clock.
+assign rst_n = ~rst;
-  logic dac_clk_in;
-  logic adc_clk_in;
-  assign dac_clk_in = ctrl_clk;
-  assign adc_clk_in = ctrl_clk;
-
-  logic finish;
-  assign finish = 1'b0;
 
   // ---------------------------------------------------------------------------
   // AXI-Lite flat -> axi4l_if
@@ -182,8 +132,8 @@ module tb_controller_dma_accum_wrapper_axil #(
     .DATA_W (AXIS_DATA_WIDTH),
     .KEEP_W (AXIS_KEEP_WIDTH),
     .ID_W   (AXIS_ID_WIDTH),
-    .DEST_W (AXIS_DEST_WIDTH),
+    .DEST_W (dma_reg_pkg::AXIS_DEST_WIDTH),
-    .USER_W (AXIS_USER_WIDTH)
+    .USER_W (dma_reg_pkg::AXIS_USER_WIDTH)
   ) dma_read_data (
     .aclk(ctrl_clk),
     .aresetn(rst_n)
@@ -195,8 +145,8 @@ axis_if_to_flat #(
     .DATA_W (AXIS_DATA_WIDTH),
     .KEEP_W (AXIS_KEEP_WIDTH),
     .ID_W   (AXIS_ID_WIDTH),
-    .DEST_W (AXIS_DEST_WIDTH),
+    .DEST_W (dma_reg_pkg::AXIS_DEST_WIDTH),
-    .USER_W (AXIS_USER_WIDTH)
+    .USER_W (dma_reg_pkg::AXIS_USER_WIDTH)
 ) u_read_data_if_to_flat (
     .s_axis(dma_read_data),
 
@@ -212,20 +162,6 @@ axis_if_to_flat #(
 );
 
 
-
-  // Controller ADC/DAC outputs.
-  logic [31:0]               adc_window_size;
-  logic [31:0]               dac_pulse_width;
-  logic [31:0]               dac_pulse_period;
-  logic [DAC_DATA_WIDTH-1:0] dac_pulse_height;
-  logic [15:0]               dac_pulse_num;
-  logic [31:0]               adc_pulse_period;
-  logic [15:0]               adc_pulse_num;
-  logic                      dac_start;
-  logic                      adc_start;
-  logic                      dac_rst;
-  logic                      adc_rst;
-
   wrapper_controller_dma_accum #(
     .ADDR_W(ADDR_W),
     .DATA_W(DATA_W),
@@ -254,26 +190,10 @@ axis_if_to_flat #(
     .rst_n(rst_n),
     .s_axil(axil_bus),
 
-    .dac_pulse_width(dac_pulse_width),
-    .dac_pulse_period(dac_pulse_period),
-    .dac_pulse_height(dac_pulse_height),
-    .dac_pulse_num(dac_pulse_num),
-
     .sampler_m_axis_tdata(sampler_m_axis_tdata),
     .sampler_m_axis_tvalid(sampler_m_axis_tvalid),
 
-    .adc_pulse_period(adc_pulse_period),
-    .adc_pulse_num(adc_pulse_num),
-
-    .dac_pulse_width(dac_pulse_width),
-    .dac_pulse_period(dac_pulse_period),
-    .dac_pulse_height(dac_pulse_height),
-    .dac_pulse_num(dac_pulse_num),
-
-    .dac_start(dac_start),
-    .dac_rst(dac_rst),
-
     .m_axis_read_data(dma_read_data)
   );
 
-endmodule : tb_controller_wrapper_axil
+endmodule : tb_controller_dma_accum_wrapper_axil

designs/controller_dma_connective/tests/dma_accum_connection/test_timing.xdc

@@ -0,0 +1,13 @@
+# Primary clocks
+create_clock -name eth_clk -period 8.000  [get_ports eth_clk_in]
+create_clock -name dac_clk -period 7.692  [get_ports dac_clk_in]
+create_clock -name adc_clk -period 15.385 [get_ports adc_clk_in]
+
+
+# Asynchronous clock groups
+# eth, dac, adc are independent domains
+
+set_clock_groups -name ASYNC_ETH_DAC_ADC -asynchronous \
+    -group [get_clocks eth_clk] \
+    -group [get_clocks dac_clk] \
+    -group [get_clocks adc_clk]