strapping for the test

designs/controller_dma_connective/src/wrapper_controller_dma_accum.sv

@@ -1,6 +1,6 @@
 import dma_reg_pkg::*;
 
-module wrapper_controller_dma_accum
+module wrapper_controller_dma_accum 
 #(
     parameter int unsigned ADDR_W             = 16,
     parameter int unsigned DATA_W             = 32,
@@ -43,29 +43,26 @@ module wrapper_controller_dma_accum
 
     // adc_clk_in domain
 
-    input logic [AXI_DATA_WIDTH-1:0]   sampler_m_axis_tdata,
+    input logic [ADC_DATA_WIDTH-1:0]   sampler_m_axis_tdata,
     input logic                        sampler_m_axis_tvalid,
 
-    // dac_clk_in domain outputs
-    output logic [31:0]                dac_pulse_width,
-    output logic [31:0]                dac_pulse_period,
-    output logic [DAC_DATA_WIDTH-1:0]  dac_pulse_height,
-    output logic [15:0]                dac_pulse_num,
-
-    // adc_clk_in domain outputs
-    output logic [31:0]                adc_pulse_period,
-    output logic [15:0]                adc_pulse_num,
-
-    // pulse outputs
-    output logic                       dac_start,
-    output logic                       dac_rst
-
     axis_if.master    m_axis_read_data
 );
 
 logic workflow_done, processing_done;
 logic [31:0] window_size;
 logic adc_start, adc_rst;
+logic [31:0]                dac_pulse_width;
+logic [31:0]                dac_pulse_period;
+logic [DAC_DATA_WIDTH-1:0]  dac_pulse_height;
+logic [15:0]                dac_pulse_num;
+
+    // adc_clk_in domain outputs
+logic [31:0]                adc_pulse_period;
+logic [15:0]                adc_pulse_num;
+
+    // pulse outputs
+logic  dac_start, dac_rst;
 
 axis_if #(
     .DATA_W($bits(dma_read_status_t)),
@@ -218,7 +215,7 @@ accumulator_top #(
     ) accumulator_top_inst (
         .clk_in(clk_sampler),
         .rst(adc_rst),
-        .s_axis_tdata(sampler_m_axis_tdata[ADC_DATA_WIDTH-1:0]),
+        .s_axis_tdata(sampler_m_axis_tdata),
         .s_axis_tvalid(sampler_m_axis_tvalid),
         .start(adc_start),
         .smp_num(adc_pulse_period),