baulin.fa/reflectometer_fpga_project
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improved readability

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otroubi
2026-07-31 17:57:35 +03:00
parent d84e809336
commit 947ba908fb
1 changed files with 2 additions and 2 deletions
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designs/full_new_reflectometer/src/reflectometer_ip.sv
+2 -2
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@@ -208,7 +208,7 @@ wire workflow_done, processing_done;
.DATA_WIDTH(ADC_DATA_WIDTH), .DATA_WIDTH(ADC_DATA_WIDTH),
.PACK_FACTOR(PACK_FACTOR), .PACK_FACTOR(PACK_FACTOR),
.PROCESS_MODE(PROCESS_MODE) .PROCESS_MODE(PROCESS_MODE)
) sampler_dut ( ) sampler_inst (
.clk_in(clk_sampler), .clk_in(clk_sampler),
.rst(adc_rst), .rst(adc_rst),
.data_in(adc_data), .data_in(adc_data),
@@ -226,7 +226,7 @@ wire workflow_done, processing_done;
.N_MAX(N_MAX), .N_MAX(N_MAX),
.PACKET_SIZE(PACKET_SIZE), .PACKET_SIZE(PACKET_SIZE),
.RW_WIDTH(RD_FIFO_WIDTH) .RW_WIDTH(RD_FIFO_WIDTH)
) dut ( ) accumulator_top_inst (
.clk_in(clk_sampler), .clk_in(clk_sampler),
.rst(!ctrl_rst_n), .rst(!ctrl_rst_n),
.s_axis_tdata(sampler_m_axis_tdata), .s_axis_tdata(sampler_m_axis_tdata),