baulin.fa/reflectometer_fpga_project
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

fix: out_axis_fifo states

Browse Source
This commit is contained in:
Phil
2026-04-28 11:56:19 +03:00
parent 9b189f931f
commit 91eaf6c4f8
1 changed files with 18 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
rtl/accum/src/out_axis_fifo.sv
View File

@ -9,10 +9,10 @@ module out_axis_fifo #(
input logic [31:0] smp_num,
// AXI stream master for output, eth_clk_in domain
output logic [7:0] s_axis_tdata,
output logic s_axis_tvalid,
input logic s_axis_tready,
output logic s_axis_tlast,
output logic [7:0] m_axis_tdata,
output logic m_axis_tvalid,
input logic m_axis_tready,
output logic m_axis_tlast,
// eth handshake
input logic req_ready,
output logic send_req,
@ -86,6 +86,8 @@ module out_axis_fifo #(
reg [31:0] wr_batch_tgt; // next 'target' that should be written from batch
reg [31:0] wr_total; // total BITS to be sent!
wire empty;
wire [WDEPTH_BITS:0] wr_data_count;
// NOTE:
@ -121,7 +123,7 @@ module out_axis_fifo #(
// wait until we can request a word
// depends on prog_full signal
WR_CHECK: begin
if (~wr_unavail && ~wr_rst_busy) begin
if ((wr_data_count < (FIFO_WDEPTH - (PACKET_SIZE / (ACCUM_WIDTH / 8)))) && ~wr_rst_busy) begin
batch_req <= 1;
// should give us exactly PACKET_SIZE * 8 bits
// multiplied by WINDOW_SIZE, because we count
@ -159,7 +161,7 @@ module out_axis_fifo #(
// wr_cnt should be by design PACKET_SIZE-aligned
if (wr_cnt >= wr_total) begin
// wait until all data is sent
if (wr_data_count == 0) begin
if (empty) begin
finish <= 1;
wr_state <= WR_IDLE;
end
@ -193,8 +195,8 @@ module out_axis_fifo #(
rd_state <= RD_IDLE;
send_req <= 1'b0;
sent_cnt <= 16'd0;
s_axis_tlast <= 1'b0;
s_axis_tvalid <= 1'b0;
m_axis_tlast <= 1'b0;
m_axis_tvalid <= 1'b0;
rd_en <= 1'b0;
end else begin
@ -209,8 +211,8 @@ module out_axis_fifo #(
send_req <= 1'b0;
sent_cnt <= 16'd0;
rd_en <= 1'b0;
s_axis_tlast <= 1'b0;
s_axis_tvalid <= 1'b0;
m_axis_tlast <= 1'b0;
m_axis_tvalid <= 1'b0;
end
// await udp ready
@ -225,18 +227,18 @@ module out_axis_fifo #(
RD_SEND: begin
// udp is ready and fifo is ready = sent
send_req <= 1'b0;
if (s_axis_tready && rd_valid) begin
if (m_axis_tready && rd_valid) begin
rd_en <= 1'b1;
s_axis_tvalid <= 1'b1;
m_axis_tvalid <= 1'b1;
sent_cnt <= sent_cnt + 1;
// final packet of the batch
if (sent_cnt == PACKET_SIZE - 1) begin
rd_state <= RD_IDLE;
s_axis_tlast <= 1'b1;
m_axis_tlast <= 1'b1;
end
end else begin
rd_en <= 1'b0;
s_axis_tvalid <= 1'b0;
m_axis_tvalid <= 1'b0;
end
end
endcase
@ -288,8 +290,8 @@ module out_axis_fifo #(
.data_valid(rd_valid), // 1-bit output: Read Data Valid: When asserted, this signal indicates that valid data is available on the
// output bus (dout).
.dout(s_axis_tdata),
.empty( ),
.dout(m_axis_tdata),
.empty(empty),
.full( ),