From 906d5090cde8bb3907a26423b19859869e6343ef Mon Sep 17 00:00:00 2001 From: "babintsev.lv" Date: Tue, 26 May 2026 18:30:51 +0300 Subject: [PATCH] reflectometer top testbench config update --- .../reflectometer_base/tb_reflectometer.sv | 144 +++++++++++++++++- 1 file changed, 136 insertions(+), 8 deletions(-) diff --git a/designs/reflectometer_base/tb_reflectometer.sv b/designs/reflectometer_base/tb_reflectometer.sv index 02d9c00..36f809c 100644 --- a/designs/reflectometer_base/tb_reflectometer.sv +++ b/designs/reflectometer_base/tb_reflectometer.sv @@ -12,9 +12,40 @@ module tb_reflectometer; localparam N_MAX = 4096; // max value of windows to average by experiments localparam WINDOW_SIZE = 65; // fixed subwindow size to average by time localparam PACKET_SIZE = 1024; // bytes per UDP packet + + localparam int unsigned ADC_CLK_MHZ = 65; + localparam int unsigned DAC_CLK_MHZ = 125; + + // may be changed for test purposes + localparam int unsigned PULSE_WIDTH = 2**6; + localparam int unsigned PULSE_PERIOD = 2**8; + localparam int unsigned PULSE_NUM = 10; + localparam int unsigned PULSE_HEIGHT = 2**12; + localparam int unsigned PULSE_PERIOD_ADC = (int'(real'(ADC_CLK_MHZ) / real'(DAC_CLK_MHZ) * real'(PULSE_PERIOD)) / int'(WINDOW_SIZE)) * int'(WINDOW_SIZE); + initial begin + if (PULSE_WIDTH <= 0) + $fatal(1, "PULSE_WIDTH should be positive"); + if (PULSE_PERIOD <= 0) + $fatal(1, "PULSE_PERIOD should be positive"); + if (PULSE_NUM <= 0) + $fatal(1, "PULSE_NUM should be positive"); + if (PULSE_HEIGHT <= 0) + $fatal(1, "PULSE_HEIGHT should be positive"); + if (PULSE_WIDTH >= 2**32-1) + $fatal(1, "PULSE_WIDTH too high"); + if (PULSE_PERIOD >= 2**32-1) + $fatal(1, "PULSE_PERIOD too high"); + if (PULSE_NUM >= 2**16-1) + $fatal(1, "PULSE_NUM too high"); + if (PULSE_HEIGHT >= 2**DAC_DATA_WIDTH-1) + $fatal(1, "PULSE_HEIGHT too high"); + if (PULSE_PERIOD_ADC % WINDOW_SIZE == 0) + $fatal(1, "PULSE_PERIOD_ADC isn't multiple of WINDOW_SIZE"); + end + // DUT signals - logic clk200, clk_eth_phy_tx, clk_eth_phy_rx; + logic clk200, clk_eth_phy_tx, clk_eth_phy_rx; // GMII clocks logic rst_n; wire [3:0] status_leds; // [ None, dac_start, m_axis_valid, clk_wiz_locked ] @@ -24,17 +55,19 @@ module tb_reflectometer; logic adc_otr; logic [ADC_DATA_WIDTH-1:0] adc_data; - wire [7:0] s_axis_tx_tdata; - wire s_axis_tx_tvalid; + wire [7:0] s_axis_tx_tdata; + wire s_axis_tx_tvalid; logic s_axis_tx_tready; - wire s_axis_tx_tlast; + wire s_axis_tx_tlast; - logic phy_ready; - wire accum_tx_start; + logic phy_ready; + wire accum_tx_start; logic [7:0] m_axis_rx_tdata; logic m_axis_rx_tvalid; logic m_axis_rx_tlast; - wire m_axis_rx_tready; + logic m_axis_rx_tready; + + logic [127:0] dut_config = 0; // DUT reflectometer_top #( @@ -101,6 +134,90 @@ module tb_reflectometer; end assign adc_otr = 1'b0; + // AXIS tasks + task automatic axis_send_byte( + ref logic clk, + input logic [7:0] data, + input logic last, + ref logic tvalid, + ref logic [7:0] tdata, + ref logic tlast, + input logic tready + ); + @(posedge clk); + tdata <= data; + tlast <= last; + tvalid <= 1'b1; + + // Ждем готовности приемника + wait(tready === 1'b1); + + @(posedge clk); + tvalid <= 1'b0; + tlast <= 1'b0; + endtask + + task automatic dut_soft_reset(); + axis_send_byte( + .clk(clk_eth_phy_rx), + .data(8'b00001111), + .last(1'b1), + .tvalid(m_axis_rx_tvalid), + .tdata(m_axis_rx_tdata), + .tlast(m_axis_rx_tlast), + .tready(m_axis_rx_tready) + ); + endtask + + task automatic dut_start(); + axis_send_byte( + .clk(clk_eth_phy_rx), + .data(8'b11110000), + .last(1'b1), + .tvalid(m_axis_rx_tvalid), + .tdata(m_axis_rx_tdata), + .tlast(m_axis_rx_tlast), + .tready(m_axis_rx_tready) + ); + endtask + +// task automatic dut_send_config( +// input logic [127:0] ctrl_config +// ); +// // команда set_data +// axis_send_byte( +// .clk(clk_eth_phy_rx), +// .data(8'b10001000), +// .last(1'b0), +// .tvalid(m_axis_rx_tvalid), +// .tdata(m_axis_rx_tdata), +// .tlast(m_axis_rx_tlast), +// .tready(m_axis_rx_tready) +// ); +// // config burst +// for (int i = 0; i < 16; i++) begin +// logic [7:0] byte_to_send; +// logic is_last; + +// // get byte +// byte_to_send = ctrl_config[i*8 +: 8]; +// // tlast for last byte +// is_last = (i == 15); + +// axis_send_byte( +// .clk(clk_eth_phy_rx), +// .data(byte_to_send), +// .last(is_last), +// .tvalid(m_axis_rx_tvalid), +// .tdata(m_axis_rx_tdata), +// .tlast(m_axis_rx_tlast), +// .tready(m_axis_rx_tready) +// ); +// end +// endtask + + + // some helpers for controller axis // GAME PLAN @@ -130,9 +247,20 @@ module tb_reflectometer; #20; $display("=== clocks ready / wiz. locked ==="); #40; + // ready to work + dut_config[31:0] = PULSE_WIDTH; + dut_config[63:32] = PULSE_PERIOD; + dut_config[79:64] = PULSE_NUM; + dut_config[79+DAC_DATA_WIDTH:80] = PULSE_HEIGHT; + dut_config[127:96] = PULSE_PERIOD_ADC; - +// dut_send_config(dut_config); + dut_start(); + // dut_start(); + #1000; + // dut_soft_reset(); + $display("=== ALL BASIC TESTS PASSED ==="); $finish; end