diff --git a/rtl/accum/src/accum.sv b/rtl/accum/src/accum.sv
index b09b838..6f171b0 100644
--- a/rtl/accum/src/accum.sv
+++ b/rtl/accum/src/accum.sv
@@ -22,7 +22,8 @@ module accumulator
     output out_valid,
     output readout_begin,
     input batch_req,
-    input finish
+    input finish,
+    output logic accum_done
     );
 
     logic [31:0] smp_num_reg, cnt_smp_num;
@@ -66,7 +67,6 @@ module accumulator
     // Then the next sequence can read the same address it is written
     logic accum_pipe_bypass_valid;
     logic [ACCUM_WIDTH-1:0] accum_pipe_bypass_data;
-    logic accum_done;
 
     logic accum_accept_last;
     logic accum_accept_last_all;
diff --git a/rtl/accum/src/accum_top.sv b/rtl/accum/src/accum_top.sv
index dc788a1..a01c8c6 100644
--- a/rtl/accum/src/accum_top.sv
+++ b/rtl/accum/src/accum_top.sv
@@ -34,7 +34,8 @@ module accumulator_top
     input  logic            m_axis_tready,
     output logic            m_axis_tlast,
 
-    output logic finish
+    output logic finish,
+    output logic accum_done
     );
 
     wire [ACCUM_WIDTH-1:0] out_data;
@@ -91,7 +92,8 @@ module accumulator_top
         .out_valid(out_valid),
         .readout_begin(readout_begin),
         .batch_req(batch_req),
-        .finish(finish_int)
+        .finish(finish_int),
+        .accum_done(accum_done)
     );
 
     out_axis_fifo #(