diff --git a/rtl/accum/src/accum.sv b/rtl/accum/src/accum.sv
index df3073b..c32ac1e 100644
--- a/rtl/accum/src/accum.sv
+++ b/rtl/accum/src/accum.sv
@@ -1,11 +1,9 @@
-`timescale 1ns / 1ps
-
 module accumulator
 #(
     parameter DATA_WIDTH = 12,
     parameter ACCUM_WIDTH = 32,
     parameter N_MAX = 4096,
-    parameter PACKET_SIZE = 256,
+    parameter PACKET_SIZE = 8,
     parameter READ_BATCH_SIZE =(PACKET_SIZE*8)/(ACCUM_WIDTH)
     )
 (
diff --git a/rtl/accum/src/accum_top.sv b/rtl/accum/src/accum_top.sv
index 22e0cea..5f0d9ea 100644
--- a/rtl/accum/src/accum_top.sv
+++ b/rtl/accum/src/accum_top.sv
@@ -25,7 +25,7 @@ module accumulator_top
     input [31:0] window_size,
 
     // eth signals
-    input eth_clk_in,
+    input dma_clk_in,
     input req_ready,
     output send_req,
 
@@ -102,7 +102,7 @@ module accumulator_top
         .PACKET_SIZE(PACKET_SIZE),
         .RW_WIDTH(RW_WIDTH)
     ) output_async_fifo (
-        .eth_clk_in    (eth_clk_in),
+        .dma_clk_in    (dma_clk_in),
         .acc_clk_in    (clk_in),
         .rst           (rst),
         .smp_num       (smp_num),
diff --git a/rtl/accum/src/out_axis_fifo.sv b/rtl/accum/src/out_axis_fifo.sv
index 2b53b1a..ecb6a8a 100644
--- a/rtl/accum/src/out_axis_fifo.sv
+++ b/rtl/accum/src/out_axis_fifo.sv
@@ -3,13 +3,13 @@ module out_axis_fifo #(
     parameter RW_WIDTH    = 32,
     parameter PACKET_SIZE = 256
 ) (
-    input  logic                eth_clk_in,
+    input  logic                dma_clk_in,
     input  logic                acc_clk_in,
     input  logic                rst,
     input  logic [31:0]         smp_num,
     input  logic [31:0]         window_size,
 
-    // AXI stream master for output, eth_clk_in domain
+    // AXI stream master for output, dma_clk_in domain
     output logic [RW_WIDTH-1:0]          m_axis_tdata,
     output logic                m_axis_tvalid,
     input  logic                m_axis_tready,
@@ -201,7 +201,7 @@ module out_axis_fifo #(
     wire rd_valid;
     wire [RDEPTH_BITS-1:0] rd_data_count;
 
-    always_ff @(posedge eth_clk_in) begin
+    always_ff @(posedge dma_clk_in) begin
         if (rst_eth) begin
             rd_state <= RD_IDLE;
             send_req <= 1'b0;
@@ -318,7 +318,7 @@ module out_axis_fifo #(
 
 
 
-        .rd_clk(eth_clk_in),               // 1-bit input: Read clock: Used for read operation. rd_clk must be a free running clock.
+        .rd_clk(dma_clk_in),               // 1-bit input: Read clock: Used for read operation. rd_clk must be a free running clock.
         .rd_en(rd_en),                 // 1-bit input: Read Enable: If the FIFO is not empty, asserting this signal causes data (on dout) to be read
                                         // from the FIFO. Must be held active-low when rd_rst_busy is active high.