Debugged modules: sampler, generator, part of the accum module.

rtl/accum/src/out_axis_fifo.sv

@@ -1,7 +1,7 @@
 module out_axis_fifo #(
     parameter ACCUM_WIDTH = 32,
     parameter RW_WIDTH    = 32,
-    parameter PACKET_SIZE = 256
+    parameter PACKET_SIZE = 64
 ) (
     input  logic                dma_clk_in,
     input  logic                acc_clk_in,
@@ -32,7 +32,7 @@ module out_axis_fifo #(
 );
     // sync reset
     reg [1:0] rst_sync_ff;
-    reg rst_eth;
+    reg rst_dma;
 
     always @(posedge acc_clk_in or posedge rst) begin
         if (rst) begin
@@ -42,7 +42,7 @@ module out_axis_fifo #(
         end
     end
 
-    assign rst_eth = rst_sync_ff[1];
+    assign rst_dma = rst_sync_ff[1];
 
     logic [1:0] rst_acc_ff;
     logic rst_acc;
@@ -199,15 +199,16 @@ module out_axis_fifo #(
     (* MARK_DEBUG="true" *) rd_state_t rd_state;
 
     wire rd_valid;
+    assign m_axis_tvalid = rd_valid;
     wire [RDEPTH_BITS-1:0] rd_data_count;
 
     always_ff @(posedge dma_clk_in) begin
-        if (rst_eth) begin
+        if (rst_dma) begin
             rd_state <= RD_IDLE;
             send_req <= 1'b0;
             sent_cnt <= 16'd0;
             m_axis_tlast <= 1'b0;
-            m_axis_tvalid <= 1'b0;
+            //m_axis_tvalid <= 1'b0;
             rd_en <= 1'b0;
             
         end else begin
@@ -215,7 +216,7 @@ module out_axis_fifo #(
             case (rd_state)
                 // wait until fifo has enough data to send
                 RD_IDLE: begin
-                    if (rd_data_count >= PACKET_RD_WORDS) begin
+                    if (rd_data_count >= 1) begin
                         // enough data to send packet, begin
                         rd_state <= RD_CHECK;
                     end
@@ -223,7 +224,7 @@ module out_axis_fifo #(
                     sent_cnt <= 16'd0;
                     rd_en <= 1'b0;
                     m_axis_tlast <= 1'b0;
-                    m_axis_tvalid <= 1'b0;
+                    //m_axis_tvalid <= 1'b0;
                 end
 
                 // await udp ready
@@ -238,20 +239,17 @@ module out_axis_fifo #(
                 RD_SEND: begin
                     // udp is ready and fifo is ready = sent
                     send_req <= 1'b0;
-                    m_axis_tvalid <= rd_valid;
+                    //m_axis_tvalid <= rd_valid;
                     rd_en <= m_axis_tvalid && m_axis_tready;
                     if (m_axis_tready && rd_valid) begin
-                        //rd_en <= 1'b1;
-                        //m_axis_tvalid <= 1'b1;
                         sent_cnt <= sent_cnt + 1;
                         // final packet of the batch
-                        if (sent_cnt == PACKET_RD_WORDS-1) begin
+                        if (sent_cnt == smp_num-1) begin
                             rd_state <= RD_IDLE;
                             m_axis_tlast <= 1'b1;
                         end
                     end else begin
                         rd_en <= 1'b0;
-                        m_axis_tvalid <= 1'b0;
                     end
                 end
             endcase

rtl/controller_new/src/controller_wrapper_axil.sv

@@ -176,8 +176,8 @@ parameter int unsigned DAC_DATA_WIDTH     = 12
 
     dma_write_status_t status_write_cmd, status_write_cmd_in;
     assign status_write_len = status_write_cmd.len;
-    assign status_write_config = { status_write_cmd.error, status_write_cmd.user, 
+    assign status_write_config = { status_write_cmd.error, 1'b0, 
-    status_write_cmd.dest, status_write_cmd.id, status_write_cmd.tag};
+    8'b0, 8'b0, status_write_cmd.tag};
 
     dma_controller dma_controller_inst
     (

rtl/generator/src/generator.sv

@@ -27,13 +27,6 @@ module generator
 
     logic enable, synced;
 
-    initial begin
-        cnt_pulse_period = '0;
-        cnt_pulse_num    = '0;
-        enable           =  0;
-        synced           =  0;
-        dac_out          = ZERO_LEVEL;
-    end
 
     always @(posedge clk_dac) begin
         if (rst) begin
@@ -92,4 +85,4 @@ module generator
             end
         end
     end
-endmodule
+endmodule

rtl/sampler/src/sampler.sv

@@ -40,11 +40,6 @@ module sampler
             end
     end
 
-    initial begin
-        synced = 0;
-        m_axis_tdata = '0;
-        m_axis_tvalid = 0;
-    end
     
     always_ff @(posedge clk_in) begin
         if (rst) begin
@@ -84,4 +79,4 @@ module sampler
             end
         end
     end    
-endmodule
+endmodule