add ram

designs/controller_dma_connective/src/axi_ram_wrapper.sv

@@ -0,0 +1,60 @@
+module axi_ram_wrapper
+#(
+    parameter int unsigned DATA_WIDTH = 32,
+    parameter int unsigned ADDR_WIDTH = 16,
+    parameter int unsigned ID_WIDTH = 8,
+    parameter int unsigned PIPELINE_OUTPUT = 0
+)
+(
+    input  logic clk,
+    input  logic rst,
+    axi4_if.slave s_axi
+);
+
+axi_ram
+#(
+    .DATA_WIDTH(DATA_WIDTH),
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .ID_WIDTH(ID_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT)
+) axi_ram_inst
+(
+    .clk(clk),
+    .rst(rst),
+    .s_axi_awid(s_axi.req.aw.id),
+    .s_axi_awaddr(s_axi.req.aw.addr),
+    .s_axi_awlen(s_axi.req.aw.len),
+    .s_axi_awsize(s_axi.req.aw.size),
+    .s_axi_awburst(s_axi.req.aw.burst),
+    .s_axi_awlock(s_axi.req.aw.lock),
+    .s_axi_awcache(s_axi.req.aw.cache),
+    .s_axi_awprot(s_axi.req.aw.prot),
+    .s_axi_awvalid(s_axi.req.aw.valid),
+    .s_axi_awready(s_axi.resp.aw_ready),
+    .s_axi_wdata(s_axi.req.w.data),
+    .s_axi_wstrb(s_axi.req.w.strb),
+    .s_axi_wlast(s_axi.req.w.last),
+    .s_axi_wvalid(s_axi.req.w.valid),
+    .s_axi_wready(s_axi.resp.w_ready),
+    .s_axi_bid(s_axi.resp.b.id),
+    .s_axi_bresp(s_axi.resp.b.resp),
+    .s_axi_bvalid(s_axi.resp.b.valid),
+    .s_axi_bready(s_axi.req.b_ready),
+    .s_axi_arid(s_axi.req.ar.id),
+    .s_axi_araddr(s_axi.req.ar.addr),
+    .s_axi_arlen(s_axi.req.ar.len),
+    .s_axi_arsize(s_axi.req.ar.size),
+    .s_axi_arburst(s_axi.req.ar.burst),
+    .s_axi_arlock(s_axi.req.ar.lock),
+    .s_axi_arcache(s_axi.req.ar.cache),
+    .s_axi_arprot(s_axi.req.ar.prot),
+    .s_axi_arvalid(s_axi.req.ar.valid),
+    .s_axi_arready(s_axi.resp.ar_ready),
+    .s_axi_rid(s_axi.resp.r.id),
+    .s_axi_rdata(s_axi.resp.r.data),
+    .s_axi_rresp(s_axi.resp.r.resp),
+    .s_axi_rlast(s_axi.resp.r.last),
+    .s_axi_rvalid(s_axi.resp.r.valid),
+    .s_axi_rready(s_axi.req.r_ready)
+);
+endmodule

designs/controller_dma_connective/src/wrapper_controller_dma.sv

@@ -24,7 +24,9 @@ module wrapper_controller_dma
     parameter int unsigned AXIS_USER_ENABLE   = 1,
 
     parameter int unsigned ENABLE_SG          = 0,
-    parameter int unsigned ENABLE_UNALIGNED   = 0
+    parameter int unsigned ENABLE_UNALIGNED   = 0,
+
+    parameter int unsigned PIPELINE_OUTPUT    = 0
 )
 (
     input  logic                       ctrl_clk,
@@ -54,9 +56,7 @@ module wrapper_controller_dma
     output logic                       adc_rst,
 
     axis_if.master    m_axis_read_data,
-    axis_if.slave   s_axis_write_data,
-
-    axi4_if.master    m_axi
+    axis_if.slave   s_axis_write_data
 );
 
 axis_if #(
@@ -138,6 +138,16 @@ controller_wrapper_axil_inst
     .m_axis_desc_write(m_axis_desc_write)
 );
 
+axi4_if #(
+    .ADDR_W(dma_reg_pkg::AXI_ADDR_WIDTH),
+    .DATA_W(AXI_DATA_WIDTH),
+    .ID_W  (AXI_ID_WIDTH),
+    .USER_W(AXI_USER_WIDTH)
+    ) m_axi (
+    .aclk(ctrl_clk),
+    .aresetn(rst_n)
+  );
+
 axi_dma_wrapper
 #(
     .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
@@ -166,4 +176,18 @@ axi_dma_wrapper_inst
     .s_axis_write_data(s_axis_write_data),
     .m_axi(m_axi)
 );
+
+axi_ram_wrapper
+#(
+    .DATA_WIDTH(AXI_DATA_WIDTH),
+    .ADDR_WIDTH(dma_reg_pkg::AXI_ADDR_WIDTH),
+    .ID_WIDTH(dma_reg_pkg::AXIS_ID_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT)
+) axi_ram_wrapper_inst
+(
+  .clk(ctrl_clk),
+  .rst(!rst_n),
+  .s_axi(m_axi)
+);
+
 endmodule