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tests: add sample project for minimal eth udp echo

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Phil
2026-03-31 15:08:12 +03:00
parent 0dd0006e47
commit 7fedc36562
3 changed files with 260 additions and 0 deletions
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47
rtl/ethernet-udp/tests/eth_minimal/Makefile Normal file
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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# FPGA settings
FPGA_PART = xc7a35tfgg484-1
FPGA_TOP = ethernet_test_minimal
FPGA_ARCH = artix7
RTL_DIR = ../../src
# Files for synthesis
SYN_FILES = ethernet_test_minimal.v
include ../../../../scripts/vivado.mk
SYN_FILES += $(sort $(shell find ../../src -type f \( -name '*.v' -o -name '*.sv' \)))
XCI_FILES = $(sort $(shell find ../../src -type f -name '*.xci'))
program: $(PROJECT).bit
echo "open_hw_manager" > program.tcl
echo "connect_hw_server" >> program.tcl
echo "open_hw_target" >> program.tcl
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
echo "program_hw_devices [current_hw_device]" >> program.tcl
echo "exit" >> program.tcl
vivado -nojournal -nolog -mode batch -source program.tcl
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
echo "exit" >> generate_mcs.tcl
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
mkdir -p rev
COUNT=100; \
while [ -e rev/$*_rev$$COUNT.bit ]; \
do COUNT=$$((COUNT+1)); done; \
COUNT=$$((COUNT-1)); \
for x in .mcs .prm; \
do cp $*$$x rev/$*_rev$$COUNT$$x; \
echo "Output: rev/$*_rev$$COUNT$$x"; done;

162
rtl/ethernet-udp/tests/eth_minimal/ethernet_test_minimal.v Normal file
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//////////////////////////////////////////////////////////////////////////////////
// //
// //
// Author: lhj //
// //
// ALINX(shanghai) Technology Co.,Ltd //
// heijin //
// WEB: http://www.alinx.com/ //
// BBS: http://www.heijin.org/ //
// //
//////////////////////////////////////////////////////////////////////////////////
// //
// Copyright (c) 2017,ALINX(shanghai) Technology Co.,Ltd //
// All rights reserved //
// //
// This source file may be used and distributed without restriction provided //
// that this copyright statement is not removed from the file and that any //
// derivative work contains the original copyright notice and the associated //
// disclaimer. //
// //
//////////////////////////////////////////////////////////////////////////////////
//================================================================================
// Revision History:
// Date By Revision Change Description
//--------------------------------------------------------------------------------
// 2019/08/19
//*******************************************************************************/
module ethernet_test_minimal
(
input sys_clk_p, //system clock positive
input sys_clk_n, //system clock negative
input rst_n, //reset ,low active
output [3:0] led, //display network rate status
output e_reset, //phy reset
output e_mdc, //phy emdio clock
inout e_mdio, //phy emdio data
output[3:0] rgmii_txd, //phy data send
output rgmii_txctl, //phy data send control
output rgmii_txc, //Clock for sending data
input[3:0] rgmii_rxd, //recieve data
input rgmii_rxctl, //Control signal for receiving data
input rgmii_rxc //Clock for recieving data
);
wire [ 7:0] gmii_txd; //gmii data
wire gmii_tx_en; //gmii send enable
wire gmii_tx_er;
wire gmii_tx_clk; //gmii send clock
wire gmii_crs;
wire gmii_col;
wire [ 7:0] gmii_rxd; //gmii recieving data
wire gmii_rx_dv; //gmii recieving data valid
wire gmii_rx_er;
wire gmii_rx_clk; //gmii recieve clock
wire [ 1:0] speed_selection; // 1x gigabit, 01 100Mbps, 00 10mbps
wire duplex_mode; // 1 full, 0 half
wire rgmii_rxcpll;
wire [31:0] pack_total_len ; //package length
wire [1:0] speed ; //net speed select
wire link ; //link status
wire e_rx_dv ;
wire [7:0] e_rxd ;
wire e_tx_en ;
wire [7:0] e_txd ;
wire e_rst_n ;
wire sys_clk ;
assign duplex_mode = 1'b1;
/*************************************************************************
generate single end clock
**************************************************************************/
IBUFDS sys_clk_ibufgds
(
.O (sys_clk ),
.I (sys_clk_p ),
.IB (sys_clk_n )
);
(* IODELAY_GROUP = "rgmii_idelay_group" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYCTRL IDELAYCTRL_inst (
.RDY(), // 1-bit output: Ready output
.REFCLK(sys_clk), // 1-bit input: Reference clock input
.RST(1'b0) // 1-bit input: Active high reset input
);
/*************************************************************************
GMII and RGMII data conversion
****************************************************************************/
util_gmii_to_rgmii util_gmii_to_rgmii_m0
(
.reset (1'b0 ),
.rgmii_td (rgmii_txd ),
.rgmii_tx_ctl (rgmii_txctl ),
.rgmii_txc (rgmii_txc ),
.rgmii_rd (rgmii_rxd ),
.rgmii_rx_ctl (rgmii_rxctl ),
.gmii_rx_clk (gmii_rx_clk ),
.gmii_txd (e_txd ),
.gmii_tx_en (e_tx_en ),
.gmii_tx_er (1'b0 ),
.gmii_tx_clk (gmii_tx_clk ),
.gmii_crs (gmii_crs ),
.gmii_col (gmii_col ),
.gmii_rxd (gmii_rxd ),
.rgmii_rxc (rgmii_rxc ),//add
.gmii_rx_dv (gmii_rx_dv ),
.gmii_rx_er (gmii_rx_er ),
.speed_selection (2'b10 ),
.duplex_mode (duplex_mode )
);
/*************************************************************************
Different conversion of GMII data according to different network speeds
****************************************************************************/
gmii_arbi arbi_inst
(
.clk (gmii_tx_clk ),
.rst_n (rst_n ),
.speed (2'b10 ),
.link (1'b1 ),
.pack_total_len (pack_total_len ),
.e_rst_n (e_rst_n ),
.gmii_rx_dv (gmii_rx_dv ),
.gmii_rxd (gmii_rxd ),
.gmii_tx_en (gmii_tx_en ),
.gmii_txd (gmii_txd ),
.e_rx_dv (e_rx_dv ),
.e_rxd (e_rxd ),
.e_tx_en (e_tx_en ),
.e_txd (e_txd )
);
/*************************************************************************
Mac layer protocol test
****************************************************************************/
mac_test mac_test0
(
.gmii_tx_clk (gmii_tx_clk ),
.gmii_rx_clk (gmii_rx_clk ) ,
.rst_n (e_rst_n ),
.pack_total_len (pack_total_len ),
.gmii_rx_dv (e_rx_dv ),
.gmii_rxd (e_rxd ),
.gmii_tx_en (gmii_tx_en ),
.gmii_txd (gmii_txd )
);
/*************************************************************************
Generate PHY reset signal
****************************************************************************/
reset reset_m0
(
.clk (sys_clk ),
.key1 (rst_n ),
.rst_n (e_reset )
);
endmodule

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rtl/ethernet-udp/tests/eth_minimal/ethernet_test_minimal.xdc Normal file
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# constrains for minimal ethernet stack
create_clock -period 5.000 [get_ports sys_clk_p]
set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
set_property PACKAGE_PIN R4 [get_ports sys_clk_p]
set_property PACKAGE_PIN T4 [get_ports sys_clk_n]
set_property PACKAGE_PIN F15 [get_ports rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
set_property PACKAGE_PIN L13 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN M13 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN K14 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN K13 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
#########################ethernet######################
create_clock -period 8.000 [get_ports rgmii_rxc]
set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_rxd[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_txd[*]}]
set_property SLEW FAST [get_ports {rgmii_txd[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports e_mdc]
set_property IOSTANDARD LVCMOS33 [get_ports e_mdio]
set_property IOSTANDARD LVCMOS33 [get_ports e_reset]
set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxc]
set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxctl]
set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txc]
set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txctl]
set_property SLEW FAST [get_ports rgmii_txc]
set_property SLEW FAST [get_ports rgmii_txctl]
set_property PACKAGE_PIN P17 [get_ports {rgmii_rxd[3]}]
set_property PACKAGE_PIN U17 [get_ports {rgmii_rxd[2]}]
set_property PACKAGE_PIN U18 [get_ports {rgmii_rxd[1]}]
set_property PACKAGE_PIN P19 [get_ports {rgmii_rxd[0]}]
set_property PACKAGE_PIN R16 [get_ports {rgmii_txd[3]}]
set_property PACKAGE_PIN R17 [get_ports {rgmii_txd[2]}]
set_property PACKAGE_PIN P16 [get_ports {rgmii_txd[1]}]
set_property PACKAGE_PIN N14 [get_ports {rgmii_txd[0]}]
set_property PACKAGE_PIN N13 [get_ports e_mdc]
set_property PACKAGE_PIN P14 [get_ports e_mdio]
set_property PACKAGE_PIN R14 [get_ports e_reset]
set_property PACKAGE_PIN V18 [get_ports rgmii_rxc]
set_property PACKAGE_PIN R19 [get_ports rgmii_rxctl]
set_property PACKAGE_PIN P15 [get_ports rgmii_txc]
set_property PACKAGE_PIN N17 [get_ports rgmii_txctl]