diff --git a/designs/full_new_reflectometer/src/axi_dma_wrapper_if.sv b/designs/full_new_reflectometer/src/axi_dma_wrapper_if.sv new file mode 100644 index 0000000..4e2db3b --- /dev/null +++ b/designs/full_new_reflectometer/src/axi_dma_wrapper_if.sv @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: MIT +// +// SystemVerilog interface wrapper around alexforencich/verilog-axi axi_dma.v. +// +// AXI memory, AXI-Stream data, DMA descriptor, and DMA status channels are all +// exposed through compact interfaces. The original Forencich core remains +// untouched and is connected through local flat wires. +`timescale 1 ns / 1 ns +`default_nettype none +import dma_reg_pkg::*; + +// DMA Specific wrappers & converters +module axi_dma_wrapper #( + parameter int unsigned AXI_DATA_WIDTH = 32, + + parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8, + parameter int unsigned AXI_ID_WIDTH = 8, + parameter int unsigned AXI_USER_WIDTH = 1, + parameter int unsigned AXI_MAX_BURST_LEN = 16, + + parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH, + parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8, + parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8, + parameter int unsigned AXIS_LAST_ENABLE = 1, + parameter int unsigned AXIS_ID_ENABLE = 1, + parameter int unsigned AXIS_DEST_ENABLE = 0, + parameter int unsigned AXIS_USER_ENABLE = 1, + + parameter int unsigned ENABLE_SG = 0, + parameter int unsigned ENABLE_UNALIGNED = 0 +)( + input logic clk, + input logic rst, + + axis_if.slave s_axis_read_desc, + + axis_if.master m_axis_read_desc_status, + + axis_if.master m_axis_read_data, + + axis_if.slave s_axis_write_desc, + + axis_if.master m_axis_write_desc_status, + + axis_if.slave s_axis_write_data, + + axi4_if.master m_axi +); + + dma_read_desc_t read_desc; + assign read_desc = dma_read_desc_t'(s_axis_read_desc.req.t.data); + + + dma_write_desc_t write_desc; + assign write_desc = dma_write_desc_t'(s_axis_write_desc.req.t.data); + + + dma_read_status_t read_status; + assign m_axis_read_desc_status.req.t.data = read_status; + logic m_axis_read_desc_status_valid; + assign m_axis_read_desc_status.req.t.valid = m_axis_read_desc_status_valid; + + + + dma_write_status_t write_status; + assign m_axis_write_desc_status.req.t.data = write_status; + logic m_axis_write_desc_status_valid; + assign m_axis_write_desc_status.req.t.valid = m_axis_write_desc_status_valid; + + + // Original DMA: flat ports only. + axi_dma #( + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_ADDR_WIDTH (dma_reg_pkg::AXI_ADDR_WIDTH), + .AXI_STRB_WIDTH (AXI_STRB_WIDTH), + .AXI_ID_WIDTH (AXI_ID_WIDTH), + .AXI_MAX_BURST_LEN (AXI_MAX_BURST_LEN), + .AXIS_DATA_WIDTH (AXIS_DATA_WIDTH), + .AXIS_KEEP_ENABLE (AXIS_KEEP_ENABLE), + .AXIS_KEEP_WIDTH (AXIS_KEEP_WIDTH), + .AXIS_LAST_ENABLE (AXIS_LAST_ENABLE), + .AXIS_ID_ENABLE (AXIS_ID_ENABLE), + .AXIS_ID_WIDTH (dma_reg_pkg::AXIS_ID_WIDTH), + .AXIS_DEST_ENABLE (AXIS_DEST_ENABLE), + .AXIS_DEST_WIDTH (dma_reg_pkg::AXIS_DEST_WIDTH), + .AXIS_USER_ENABLE (AXIS_USER_ENABLE), + .AXIS_USER_WIDTH (dma_reg_pkg::AXIS_USER_WIDTH), + .LEN_WIDTH (dma_reg_pkg::LEN_WIDTH), + .TAG_WIDTH (dma_reg_pkg::TAG_WIDTH), + .ENABLE_SG (ENABLE_SG), + .ENABLE_UNALIGNED (ENABLE_UNALIGNED) + ) i_axi_dma ( + .clk (clk), + .rst (rst), + + .s_axis_read_desc_addr (read_desc.addr), + .s_axis_read_desc_len (read_desc.len), + .s_axis_read_desc_tag (read_desc.tag), + .s_axis_read_desc_id (read_desc.id), + .s_axis_read_desc_dest (read_desc.dest), + .s_axis_read_desc_user (read_desc.user), + .s_axis_read_desc_valid (s_axis_read_desc.req.t.valid), + .s_axis_read_desc_ready (s_axis_read_desc.resp.ready), + + .m_axis_read_desc_status_tag (read_status.tag), + .m_axis_read_desc_status_error (read_status.error), + .m_axis_read_desc_status_valid (m_axis_read_desc_status_valid), + + .m_axis_read_data_tdata (m_axis_read_data.req.t.data), + .m_axis_read_data_tkeep (m_axis_read_data.req.t.keep), + .m_axis_read_data_tvalid (m_axis_read_data.req.t.valid), + .m_axis_read_data_tready (m_axis_read_data.resp.ready), + .m_axis_read_data_tlast (m_axis_read_data.req.t.last), + .m_axis_read_data_tid (m_axis_read_data.req.t.id), + .m_axis_read_data_tdest (m_axis_read_data.req.t.dest), + .m_axis_read_data_tuser (m_axis_read_data.req.t.user), + + .s_axis_write_desc_addr (write_desc.addr), + .s_axis_write_desc_len (write_desc.len), + .s_axis_write_desc_tag (write_desc.tag), + .s_axis_write_desc_valid (s_axis_write_desc.req.t.valid), + .s_axis_write_desc_ready (s_axis_write_desc.resp.ready), + + .m_axis_write_desc_status_len (write_status.len), + .m_axis_write_desc_status_tag (write_status.tag), + .m_axis_write_desc_status_id (write_status.id), + .m_axis_write_desc_status_dest (write_status.dest), + .m_axis_write_desc_status_user (write_status.user), + .m_axis_write_desc_status_error (write_status.error), + .m_axis_write_desc_status_valid (m_axis_write_desc_status_valid), + + .s_axis_write_data_tdata (s_axis_write_data.req.t.data), + .s_axis_write_data_tkeep (s_axis_write_data.req.t.keep), + .s_axis_write_data_tvalid (s_axis_write_data.req.t.valid), + .s_axis_write_data_tready (s_axis_write_data.resp.ready), + .s_axis_write_data_tlast (s_axis_write_data.req.t.last), + .s_axis_write_data_tid (s_axis_write_data.req.t.id), + .s_axis_write_data_tdest (s_axis_write_data.req.t.dest), + .s_axis_write_data_tuser (s_axis_write_data.req.t.user), + + .m_axi_awid (m_axi.req.aw.id), + .m_axi_awaddr (m_axi.req.aw.addr), + .m_axi_awlen (m_axi.req.aw.len), + .m_axi_awsize (m_axi.req.aw.size), + .m_axi_awburst (m_axi.req.aw.burst), + .m_axi_awlock (m_axi.req.aw.lock), + .m_axi_awcache (m_axi.req.aw.cache), + .m_axi_awprot (m_axi.req.aw.prot), + .m_axi_awvalid (m_axi.req.aw.valid), + .m_axi_awready (m_axi.resp.aw_ready), + + .m_axi_wdata (m_axi.req.w.data), + .m_axi_wstrb (m_axi.req.w.strb), + .m_axi_wlast ( m_axi.req.w.last), + .m_axi_wvalid (m_axi.req.w.valid), + .m_axi_wready (m_axi.resp.w_ready), + + .m_axi_bid (m_axi.resp.b.id), + .m_axi_bresp (m_axi.resp.b.resp), + .m_axi_bvalid (m_axi.resp.b.valid), + .m_axi_bready (m_axi.req.b_ready), + + .m_axi_arid (m_axi.req.ar.id), + .m_axi_araddr (m_axi.req.ar.addr), + .m_axi_arlen (m_axi.req.ar.len), + .m_axi_arsize (m_axi.req.ar.size), + .m_axi_arburst (m_axi.req.ar.burst), + .m_axi_arlock (m_axi.req.ar.lock), + .m_axi_arcache (m_axi.req.ar.cache), + .m_axi_arprot (m_axi.req.ar.prot), + .m_axi_arvalid (m_axi.req.ar.valid), + .m_axi_arready (m_axi.resp.ar_ready), + + .m_axi_rid (m_axi.resp.r.id), + .m_axi_rdata (m_axi.resp.r.data), + .m_axi_rresp (m_axi.resp.r.resp), + .m_axi_rlast (m_axi.resp.r.last), + .m_axi_rvalid (m_axi.resp.r.valid), + .m_axi_rready (m_axi.req.r_ready), + + .read_enable (1'b1), + .write_enable (1'b1), + .write_abort (1'b0) + ); + + +endmodule : axi_dma_wrapper + +`default_nettype wire diff --git a/designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv b/designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv index f499762..011862f 100644 --- a/designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv +++ b/designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv @@ -1,3 +1,5 @@ +`timescale 1 ns / 1 ns + module reflectometer_and_dma_wrapper #( // parameters for base reflectometer works @@ -44,8 +46,8 @@ module reflectometer_and_dma_wrapper output wire locked, axi4l_if.slave s_axil, - axi4_if.master m_axi, - axi4s_if.master m_axis_read_data, + axi_if.master m_axi, + axis_if.master m_axis_read_data, // DAC output wire dac_clk_o, @@ -175,4 +177,4 @@ module reflectometer_and_dma_wrapper .m_axi(m_axi) ); -endmodule \ No newline at end of file +endmodule : reflectometer_and_dma_wrapper \ No newline at end of file