baulin.fa/reflectometer_fpga_project
2
0
Fork 0
Code Issues 4 Pull Requests Actions Packages Projects Releases Wiki Activity

full new reflectometer without clk_wizard and reset generator

Browse Source
This commit is contained in:
otroubi
2026-09-03 17:50:41 +03:00
parent e26d09e89f
commit 7c94cbca56
5 changed files with 785 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
designs/full_new_reflectometer_without_clk_wiz/src/axi_dma_wrapper_if.sv
+199
View File
@@ -0,0 +1,199 @@
// SPDX-License-Identifier: MIT
//
// SystemVerilog interface wrapper around alexforencich/verilog-axi axi_dma.v.
//
// AXI memory, AXI-Stream data, DMA descriptor, and DMA status channels are all
// exposed through compact interfaces. The original Forencich core remains
// untouched and is connected through local flat wires.
import dma_reg_pkg::*;
import axi_pkg::*;
// DMA Specific wrappers & converters
module axi_dma_wrapper #(
parameter int unsigned AXI_DATA_WIDTH = 32,
parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
parameter int unsigned AXI_ID_WIDTH = 8,
parameter int unsigned AXI_USER_WIDTH = 1,
parameter int unsigned AXI_MAX_BURST_LEN = 16,
parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
parameter int unsigned AXIS_LAST_ENABLE = 1,
parameter int unsigned AXIS_ID_ENABLE = 1,
parameter int unsigned AXIS_DEST_ENABLE = 0,
parameter int unsigned AXIS_USER_ENABLE = 1,
parameter int unsigned ENABLE_SG = 0,
parameter int unsigned ENABLE_UNALIGNED = 0
)(
input logic clk,
input logic rst,
axis_if.slave s_axis_read_desc,
axis_if.master m_axis_read_desc_status,
axis_if.master m_axis_read_data,
axis_if.slave s_axis_write_desc,
axis_if.master m_axis_write_desc_status,
axis_if.slave s_axis_write_data,
axi4_if.master m_axi
);
dma_read_desc_t read_desc;
assign read_desc = dma_read_desc_t'(s_axis_read_desc.req.t.data);
dma_write_desc_t write_desc;
assign write_desc = dma_write_desc_t'(s_axis_write_desc.req.t.data);
dma_read_status_t read_status;
assign m_axis_read_desc_status.req.t.data = read_status;
logic m_axis_read_desc_status_valid;
assign m_axis_read_desc_status.req.t.valid = m_axis_read_desc_status_valid;
dma_write_status_t write_status;
assign m_axis_write_desc_status.req.t.data = write_status;
logic m_axis_write_desc_status_valid;
assign m_axis_write_desc_status.req.t.valid = m_axis_write_desc_status_valid;
logic [1:0] dma_awburst;
logic [1:0] dma_arburst;
logic [1:0] dma_bresp;
logic [1:0] dma_rresp;
assign m_axi.req.aw.burst = axi_pkg::axi_burst_t'(dma_awburst);
assign m_axi.req.ar.burst = axi_pkg::axi_burst_t'(dma_arburst);
assign dma_bresp = logic'(m_axi.resp.b.resp);
assign dma_rresp = logic'(m_axi.resp.r.resp);
// Original DMA: flat ports only.
axi_dma #(
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH (dma_reg_pkg::AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH (AXI_STRB_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN (AXI_MAX_BURST_LEN),
.AXIS_DATA_WIDTH (AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE (AXIS_KEEP_ENABLE),
.AXIS_KEEP_WIDTH (AXIS_KEEP_WIDTH),
.AXIS_LAST_ENABLE (AXIS_LAST_ENABLE),
.AXIS_ID_ENABLE (AXIS_ID_ENABLE),
.AXIS_ID_WIDTH (dma_reg_pkg::AXIS_ID_WIDTH),
.AXIS_DEST_ENABLE (AXIS_DEST_ENABLE),
.AXIS_DEST_WIDTH (dma_reg_pkg::AXIS_DEST_WIDTH),
.AXIS_USER_ENABLE (AXIS_USER_ENABLE),
.AXIS_USER_WIDTH (dma_reg_pkg::AXIS_USER_WIDTH),
.LEN_WIDTH (dma_reg_pkg::LEN_WIDTH),
.TAG_WIDTH (dma_reg_pkg::TAG_WIDTH),
.ENABLE_SG (ENABLE_SG),
.ENABLE_UNALIGNED (ENABLE_UNALIGNED)
) i_axi_dma (
.clk (clk),
.rst (rst),
.s_axis_read_desc_addr (read_desc.addr),
.s_axis_read_desc_len (read_desc.len),
.s_axis_read_desc_tag (read_desc.tag),
.s_axis_read_desc_id (read_desc.id),
.s_axis_read_desc_dest (read_desc.dest),
.s_axis_read_desc_user (read_desc.user),
.s_axis_read_desc_valid (s_axis_read_desc.req.t.valid),
.s_axis_read_desc_ready (s_axis_read_desc.resp.ready),
.m_axis_read_desc_status_tag (read_status.tag),
.m_axis_read_desc_status_error (read_status.error),
.m_axis_read_desc_status_valid (m_axis_read_desc_status_valid),
.m_axis_read_data_tdata (m_axis_read_data.req.t.data),
.m_axis_read_data_tkeep (m_axis_read_data.req.t.keep),
.m_axis_read_data_tvalid (m_axis_read_data.req.t.valid),
.m_axis_read_data_tready (m_axis_read_data.resp.ready),
.m_axis_read_data_tlast (m_axis_read_data.req.t.last),
.m_axis_read_data_tid (m_axis_read_data.req.t.id),
.m_axis_read_data_tdest (m_axis_read_data.req.t.dest),
.m_axis_read_data_tuser (m_axis_read_data.req.t.user),
.s_axis_write_desc_addr (write_desc.addr),
.s_axis_write_desc_len (write_desc.len),
.s_axis_write_desc_tag (write_desc.tag),
.s_axis_write_desc_valid (s_axis_write_desc.req.t.valid),
.s_axis_write_desc_ready (s_axis_write_desc.resp.ready),
.m_axis_write_desc_status_len (write_status.len),
.m_axis_write_desc_status_tag (write_status.tag),
.m_axis_write_desc_status_id (write_status.id),
.m_axis_write_desc_status_dest (write_status.dest),
.m_axis_write_desc_status_user (write_status.user),
.m_axis_write_desc_status_error (write_status.error),
.m_axis_write_desc_status_valid (m_axis_write_desc_status_valid),
.s_axis_write_data_tdata (s_axis_write_data.req.t.data),
.s_axis_write_data_tkeep (s_axis_write_data.req.t.keep),
.s_axis_write_data_tvalid (s_axis_write_data.req.t.valid),
.s_axis_write_data_tready (s_axis_write_data.resp.ready),
.s_axis_write_data_tlast (s_axis_write_data.req.t.last),
.s_axis_write_data_tid (s_axis_write_data.req.t.id),
.s_axis_write_data_tdest (s_axis_write_data.req.t.dest),
.s_axis_write_data_tuser (s_axis_write_data.req.t.user),
.m_axi_awid (m_axi.req.aw.id),
.m_axi_awaddr (m_axi.req.aw.addr),
.m_axi_awlen (m_axi.req.aw.len),
.m_axi_awsize (m_axi.req.aw.size),
.m_axi_awburst (dma_awburst),
.m_axi_awlock (m_axi.req.aw.lock),
.m_axi_awcache (m_axi.req.aw.cache),
.m_axi_awprot (m_axi.req.aw.prot),
.m_axi_awvalid (m_axi.req.aw.valid),
.m_axi_awready (m_axi.resp.aw_ready),
.m_axi_wdata (m_axi.req.w.data),
.m_axi_wstrb (m_axi.req.w.strb),
.m_axi_wlast ( m_axi.req.w.last),
.m_axi_wvalid (m_axi.req.w.valid),
.m_axi_wready (m_axi.resp.w_ready),
.m_axi_bid (m_axi.resp.b.id),
.m_axi_bresp (dma_bresp),
.m_axi_bvalid (m_axi.resp.b.valid),
.m_axi_bready (m_axi.req.b_ready),
.m_axi_arid (m_axi.req.ar.id),
.m_axi_araddr (m_axi.req.ar.addr),
.m_axi_arlen (m_axi.req.ar.len),
.m_axi_arsize (m_axi.req.ar.size),
.m_axi_arburst (dma_arburst),
.m_axi_arlock (m_axi.req.ar.lock),
.m_axi_arcache (m_axi.req.ar.cache),
.m_axi_arprot (m_axi.req.ar.prot),
.m_axi_arvalid (m_axi.req.ar.valid),
.m_axi_arready (m_axi.resp.ar_ready),
.m_axi_rid (m_axi.resp.r.id),
.m_axi_rdata (m_axi.resp.r.data),
.m_axi_rresp (dma_rresp),
.m_axi_rlast (m_axi.resp.r.last),
.m_axi_rvalid (m_axi.resp.r.valid),
.m_axi_rready (m_axi.req.r_ready),
.read_enable (1'b1),
.write_enable (1'b1),
.write_abort (1'b0)
);
endmodule : axi_dma_wrapper
`default_nettype wire
designs/full_new_reflectometer_without_clk_wiz/src/axi_ram_wrapper.sv
+67
View File
@@ -0,0 +1,67 @@
module axi_ram_wrapper
#(
parameter int unsigned DATA_WIDTH = 32,
parameter int unsigned ADDR_WIDTH = 16,
parameter int unsigned ID_WIDTH = 8,
parameter int unsigned PIPELINE_OUTPUT = 0
)
(
input logic clk,
input logic rst,
axi4_if.slave s_axi
);
logic [1:0] ram_bresp;
logic [1:0] ram_rresp;
assign s_axi.resp.b.resp = axi_pkg::axi_resp_t'(ram_bresp);
assign s_axi.resp.r.resp = axi_pkg::axi_resp_t'(ram_rresp);
axi_ram
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.ID_WIDTH(ID_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
) axi_ram_inst
(
.clk(clk),
.rst(rst),
.s_axi_awid(s_axi.req.aw.id),
.s_axi_awaddr(s_axi.req.aw.addr),
.s_axi_awlen(s_axi.req.aw.len),
.s_axi_awsize(s_axi.req.aw.size),
.s_axi_awburst(s_axi.req.aw.burst),
.s_axi_awlock(s_axi.req.aw.lock),
.s_axi_awcache(s_axi.req.aw.cache),
.s_axi_awprot(s_axi.req.aw.prot),
.s_axi_awvalid(s_axi.req.aw.valid),
.s_axi_awready(s_axi.resp.aw_ready),
.s_axi_wdata(s_axi.req.w.data),
.s_axi_wstrb(s_axi.req.w.strb),
.s_axi_wlast(s_axi.req.w.last),
.s_axi_wvalid(s_axi.req.w.valid),
.s_axi_wready(s_axi.resp.w_ready),
.s_axi_bid(s_axi.resp.b.id),
.s_axi_bresp(ram_bresp),
.s_axi_bvalid(s_axi.resp.b.valid),
.s_axi_bready(s_axi.req.b_ready),
.s_axi_arid(s_axi.req.ar.id),
.s_axi_araddr(s_axi.req.ar.addr),
.s_axi_arlen(s_axi.req.ar.len),
.s_axi_arsize(s_axi.req.ar.size),
.s_axi_arburst(s_axi.req.ar.burst),
.s_axi_arlock(s_axi.req.ar.lock),
.s_axi_arcache(s_axi.req.ar.cache),
.s_axi_arprot(s_axi.req.ar.prot),
.s_axi_arvalid(s_axi.req.ar.valid),
.s_axi_arready(s_axi.resp.ar_ready),
.s_axi_rid(s_axi.resp.r.id),
.s_axi_rdata(s_axi.resp.r.data),
.s_axi_rresp(ram_rresp),
.s_axi_rlast(s_axi.resp.r.last),
.s_axi_rvalid(s_axi.resp.r.valid),
.s_axi_rready(s_axi.req.r_ready)
);
endmodule
designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_and_dma_wrapper.sv
+173
View File
@@ -0,0 +1,173 @@
`timescale 1 ns / 1 ns
module reflectometer_and_dma_wrapper
#(
// parameters for base reflectometer works
parameter int unsigned DAC_DATA_WIDTH = 14,
parameter int unsigned ADC_DATA_WIDTH = 12,
parameter int unsigned PACK_FACTOR = 1,
parameter int unsigned PROCESS_MODE = 0,
parameter int unsigned ZERO_LEVEL = 8192,
parameter int unsigned ACCUM_WIDTH = 32,
parameter int unsigned N_MAX = 4096,
parameter int unsigned PACKET_SIZE = 1024,
parameter int unsigned RD_FIFO_WIDTH = 32,
// parameters for DMA and interfaces
parameter int unsigned ADDR_W = 16,
parameter int unsigned DATA_W = 32,
parameter int unsigned USER_W = 1,
parameter int unsigned AXI_DATA_WIDTH = 32,
parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
parameter int unsigned AXI_USER_WIDTH = 1,
parameter int unsigned AXI_MAX_BURST_LEN = 16,
parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
parameter int unsigned AXIS_LAST_ENABLE = 1,
parameter int unsigned AXIS_ID_ENABLE = 1,
parameter int unsigned AXIS_DEST_ENABLE = 0,
parameter int unsigned AXIS_USER_ENABLE = 1,
parameter int unsigned ENABLE_SG = 0,
parameter int unsigned ENABLE_UNALIGNED = 0,
parameter int unsigned PIPELINE_OUTPUT = 0
)
(
input logic ctrl_clk,
input logic clk_sampler,
input logic clk_generator,
input logic ctrl_rst_n,
axi4l_if.slave s_axil,
axi4_if.master m_axi,
// todo
axis_if.master m_axis_read_data,
// DAC
output wire [DAC_DATA_WIDTH-1:0] dac_data,
// ADC
input wire [ADC_DATA_WIDTH-1:0] adc_data,
input wire adc_otr
);
axis_if #(
.DATA_W($bits(dma_read_status_t)),
.KEEP_W(($bits(dma_read_status_t)+7)/8),
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
) s_axis_status_read (
.aclk(ctrl_clk),
.aresetn(ctrl_rst_n)
);
axis_if #(
.DATA_W($bits(dma_write_status_t)),
.KEEP_W(($bits(dma_write_status_t)+7)/8),
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
) s_axis_status_write (
.aclk(ctrl_clk),
.aresetn(ctrl_rst_n)
);
axis_if #(
.DATA_W($bits(dma_read_desc_t)),
.KEEP_W(($bits(dma_read_desc_t)+7)/8),
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
) m_axis_desc_read (
.aclk(ctrl_clk),
.aresetn(ctrl_rst_n)
);
axis_if #(
.DATA_W($bits(dma_write_desc_t)),
.KEEP_W(($bits(dma_write_desc_t)+7)/8),
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
) m_axis_desc_write (
.aclk(ctrl_clk),
.aresetn(ctrl_rst_n)
);
axis_if #(
.DATA_W(RD_FIFO_WIDTH),
.KEEP_W((RD_FIFO_WIDTH+7)/8),
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
) m_axis_accum (
.aclk(ctrl_clk),
.aresetn(ctrl_rst_n)
);
reflectometer_ip #(
.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
.PACK_FACTOR(PACK_FACTOR),
.PROCESS_MODE(PROCESS_MODE),
.ZERO_LEVEL(ZERO_LEVEL),
.ACCUM_WIDTH(ACCUM_WIDTH),
.N_MAX(N_MAX),
.PACKET_SIZE(PACKET_SIZE),
.RD_FIFO_WIDTH(RD_FIFO_WIDTH)
) reflectometer_ip_inst (
.ctrl_clk(ctrl_clk),
.clk_sampler(clk_sampler),
.clk_generator(clk_generator),
.ctrl_rst_n(ctrl_rst_n),
.s_axil(s_axil),
.m_axis_accum(m_axis_accum),
.s_axis_status_read(s_axis_status_read),
.s_axis_status_write(s_axis_status_write),
.m_axis_desc_read(m_axis_desc_read),
.m_axis_desc_write(m_axis_desc_write),
.dac_data(dac_data),
.adc_data(adc_data),
.adc_otr(adc_otr)
);
//------------------------------------------------------------
// DMA
//------------------------------------------------------------
axi_dma_wrapper #(
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_USER_WIDTH(AXI_USER_WIDTH),
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
.AXIS_ID_ENABLE(AXIS_ID_ENABLE),
.AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
.AXIS_USER_ENABLE(AXIS_USER_ENABLE),
.ENABLE_SG(ENABLE_SG),
.ENABLE_UNALIGNED(ENABLE_UNALIGNED)
) axi_dma_wrapper_inst
(
.clk(ctrl_clk),
.rst(!ctrl_rst_n),
.s_axis_read_desc(m_axis_desc_read),
.m_axis_read_desc_status(s_axis_status_read),
.m_axis_read_data(m_axis_read_data),
.s_axis_write_desc(m_axis_desc_write),
.m_axis_write_desc_status(s_axis_status_write),
.s_axis_write_data(m_axis_accum),
.m_axi(m_axi)
);
endmodule : reflectometer_and_dma_wrapper
designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_ip.sv
+207
View File
@@ -0,0 +1,207 @@
`timescale 1 ns / 1 ns
module reflectometer_ip #(
// parameters for base reflectometer works
parameter int unsigned DAC_DATA_WIDTH = 14,
parameter int unsigned ADC_DATA_WIDTH = 12,
parameter int unsigned PACK_FACTOR = 1,
parameter int unsigned PROCESS_MODE = 0,
parameter int unsigned ZERO_LEVEL = 8192,
parameter int unsigned ACCUM_WIDTH = 32,
parameter int unsigned N_MAX = 4096,
parameter int unsigned PACKET_SIZE = 1024,
parameter int unsigned RD_FIFO_WIDTH = 32,
// parameters for DMA and interfaces
parameter int unsigned ADDR_W = 16,
parameter int unsigned DATA_W = 32,
parameter int unsigned USER_W = 1
)
(
input logic ctrl_clk,
input logic clk_sampler,
input logic clk_generator,
input logic ctrl_rst_n,
axi4l_if.slave s_axil,
axis_if.master m_axis_accum,
axis_if.slave s_axis_status_read,
axis_if.slave s_axis_status_write,
axis_if.master m_axis_desc_read,
axis_if.master m_axis_desc_write,
// DAC
output wire [DAC_DATA_WIDTH-1:0] dac_data,
// ADC
input wire [ADC_DATA_WIDTH-1:0] adc_data,
input wire adc_otr
);
wire workflow_done, processing_done;
// -------------------------------------------------------------------------
// Controller
// -------------------------------------------------------------------------
wire [31:0] dac_pulse_width;
wire [31:0] dac_pulse_period;
wire [DAC_DATA_WIDTH-1:0] dac_pulse_height;
wire [15:0] dac_pulse_num;
wire [31:0] adc_pulse_period;
wire [15:0] adc_pulse_num;
wire [31:0] adc_window_size;
wire dac_start;
wire adc_start;
wire dac_rst;
wire adc_rst;
controller_wrapper_axil #(
.ADDR_W(ADDR_W),
.DATA_W(DATA_W),
.USER_W(USER_W),
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
) controller_wrapper_axil_inst
(
.ctrl_clk(ctrl_clk),
.dac_clk_in(clk_generator),
.adc_clk_in(clk_sampler),
.rst_n(ctrl_rst_n),
.s_axil(s_axil),
.workflow_done(workflow_done),
.processing_done(processing_done),
.adc_window_size(adc_window_size),
.dac_pulse_width(dac_pulse_width),
.dac_pulse_period(dac_pulse_period),
.dac_pulse_height(dac_pulse_height),
.dac_pulse_num(dac_pulse_num),
.adc_pulse_period(adc_pulse_period),
.adc_pulse_num(adc_pulse_num),
.dac_start(dac_start),
.adc_start(adc_start),
.dac_rst(dac_rst),
.adc_rst(adc_rst),
.s_axis_status_read(s_axis_status_read),
.s_axis_status_write(s_axis_status_write),
.m_axis_desc_read(m_axis_desc_read),
.m_axis_desc_write(m_axis_desc_write)
);
//------------------------------------------------------------
// DAC -> ADC CDC
//------------------------------------------------------------
(* ASYNC_REG = "TRUE" *) logic [2:0] stretch; // 125/65~=2. Чтобы поймать единичный импульс, растянем его во времени
(* ASYNC_REG = "TRUE" *) logic [1:0] sync_DA;
wire dac_done_stretched;
wire generator_done, generator_request;
wire sampler_done, sampler_request;
always_ff @(posedge clk_generator or posedge dac_rst)
begin
if (dac_rst)
stretch <= 0;
else begin
stretch[0] <= generator_done;
stretch[1] <= stretch[0];
stretch[2] <= stretch[1];
end
end
assign dac_done_stretched = |stretch;
always_ff @(posedge clk_sampler or posedge adc_rst) begin
if (adc_rst)
sync_DA <= 0;
else begin
sync_DA[0] <= dac_done_stretched;
sync_DA[1] <= sync_DA[0];
end
end
assign sampler_request = sync_DA[1];
//------------------------------------------------------------
// ADC -> DAC CDC
//------------------------------------------------------------
(* ASYNC_REG = "TRUE" *) logic [1:0] sync_AD;
always_ff @(posedge clk_generator or posedge dac_rst) begin
if (dac_rst)
sync_AD <= 0;
else begin
sync_AD[0] <= sampler_done;
sync_AD[1] <= sync_AD[0];
end
end
assign generator_request = sync_AD[1];
//------------------------------------------------------------
// Generator (DAC)
//------------------------------------------------------------
generator #(
.DATA_WIDTH(DAC_DATA_WIDTH),
.ZERO_LEVEL(ZERO_LEVEL)
) generator_inst (
.clk_dac(clk_generator),
.rst(dac_rst),
.start(dac_start),
.pulse_width(dac_pulse_width),
.pulse_period(dac_pulse_period),
.pulse_height(dac_pulse_height),
.pulse_num(dac_pulse_num),
.dac_out(dac_data),
.done(generator_done),
.request(generator_request)
);
// -------------------------------------------------------------------------
// Sampler (ADC)
// -------------------------------------------------------------------------
wire [ADC_DATA_WIDTH*PACK_FACTOR-1:0] sampler_m_axis_tdata;
wire sampler_m_axis_tvalid;
sampler #(
.DATA_WIDTH(ADC_DATA_WIDTH),
.PACK_FACTOR(PACK_FACTOR),
.PROCESS_MODE(PROCESS_MODE)
) sampler_inst (
.clk_in(clk_sampler),
.rst(adc_rst),
.data_in(adc_data),
.out_of_range(adc_otr),
.m_axis_tdata(sampler_m_axis_tdata),
.m_axis_tvalid(sampler_m_axis_tvalid),
.smp_num(adc_pulse_period),
.done(sampler_done),
.request(sampler_request)
);
accumulator_top #(
.DATA_WIDTH(ADC_DATA_WIDTH),
.ACCUM_WIDTH(ACCUM_WIDTH),
.N_MAX(N_MAX),
.PACKET_SIZE(PACKET_SIZE),
.RW_WIDTH(RD_FIFO_WIDTH)
) accumulator_top_inst (
.clk_in(clk_sampler),
.rst(adc_rst),
.s_axis_tdata(sampler_m_axis_tdata),
.s_axis_tvalid(sampler_m_axis_tvalid),
.start(adc_start),
.smp_num(adc_pulse_period),
.seq_num(adc_pulse_num),
.window_size(adc_window_size),
.dma_clk_in(ctrl_clk),
.req_ready(1'b1),
.m_axis_accum(m_axis_accum),
.finish(workflow_done),
.accum_done(processing_done)
);
endmodule
designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_top.sv
+139
View File
@@ -0,0 +1,139 @@
module reflectometer_top
#(
// parameters for base reflectometer works
parameter int unsigned DAC_DATA_WIDTH = 14,
parameter int unsigned ADC_DATA_WIDTH = 12,
parameter int unsigned PACK_FACTOR = 1,
parameter int unsigned PROCESS_MODE = 0,
parameter int unsigned ZERO_LEVEL = 8192,
parameter int unsigned ACCUM_WIDTH = 32,
parameter int unsigned N_MAX = 4096,
parameter int unsigned PACKET_SIZE = 64,
parameter int unsigned RD_FIFO_WIDTH = 32,
// parameters for DMA and interfaces
parameter int unsigned ADDR_W = 16,
parameter int unsigned DATA_W = 32,
parameter int unsigned USER_W = 1,
parameter int unsigned AXI_DATA_WIDTH = 32,
parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
parameter int unsigned AXI_USER_WIDTH = 1,
parameter int unsigned AXI_MAX_BURST_LEN = 16,
parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
parameter int unsigned AXIS_LAST_ENABLE = 1,
parameter int unsigned AXIS_ID_ENABLE = 1,
parameter int unsigned AXIS_DEST_ENABLE = 0,
parameter int unsigned AXIS_USER_ENABLE = 1,
parameter int unsigned ENABLE_SG = 0,
parameter int unsigned ENABLE_UNALIGNED = 0,
parameter int unsigned PIPELINE_OUTPUT = 0
)
(
input logic ctrl_clk,
input logic rst_n,
output wire locked,
axi4l_if.slave s_axil,
axi4_if.master m_axi,
// todo
axis_if.master m_axis_read_data,
// DAC
output wire dac_clk_o,
output wire [DAC_DATA_WIDTH-1:0] dac_data,
output wire dac_wrt,
// ADC
output wire adc_clk_o,
input wire [ADC_DATA_WIDTH-1:0] adc_data,
input wire adc_otr
);
// -------------------------------------------------------------------------
// Generated clocks for controller
// Need to create this IP in Vivado:
// input resetn
// input clk_200 : 200 MHz : Reference clock
// output clk_adc_65 : 65 MHz : ADC RTL clock
// output clk_adc_65_180 : 65 MHz, phase 180 deg. : ADC PHY clock
// output clk_adc_125 : 125 MHz : DAC RTL clock
// output clk_adc_125_180 : 125 MHz, phase 180 deg. : DAC PHY clock
// output locked
// -------------------------------------------------------------------------
wire clk_sampler, clk_generator, clk_locked;
clk_wiz_0 clk_wiz_inst
(
// Clock in ports
.clk_200(ctrl_clk),
// Clock out ports
.clk_adc_65(clk_sampler),
.clk_adc_65_180(adc_clk_o),
.clk_dac_125(clk_generator),
.clk_dac_125_180(dac_clk_o),
// Status and control signals
.reset(~rst_n),
.locked(clk_locked)
);
assign locked = clk_locked;
// -------------------------------------------------------------------------
// Controller reset
// Use both external reset and clk_wiz lock
// -------------------------------------------------------------------------
wire ctrl_rst_n = rst_n & clk_locked;
assign dac_wrt = dac_clk_o;
reflectometer_and_dma_wrapper
#(
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_USER_WIDTH(AXI_USER_WIDTH),
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
.AXIS_ID_ENABLE(AXIS_ID_ENABLE),
.AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
.AXIS_USER_ENABLE(AXIS_USER_ENABLE),
.ENABLE_SG(ENABLE_SG),
.ENABLE_UNALIGNED(ENABLE_UNALIGNED),
.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
.PACK_FACTOR(PACK_FACTOR),
.PROCESS_MODE(PROCESS_MODE),
.ZERO_LEVEL(ZERO_LEVEL),
.ACCUM_WIDTH(ACCUM_WIDTH),
.N_MAX(N_MAX),
.PACKET_SIZE(PACKET_SIZE),
.RD_FIFO_WIDTH(RD_FIFO_WIDTH)
) reflectometer_and_dma_wrapper_inst
(
.ctrl_clk(ctrl_clk),
.clk_sampler(clk_sampler),
.clk_generator(clk_generator),
.ctrl_rst_n(ctrl_rst_n),
.s_axil(s_axil),
.m_axi(m_axi),
.m_axis_read_data(m_axis_read_data),
.dac_data(dac_data),
.adc_data(adc_data),
.adc_otr(adc_otr)
);
endmodule