baulin.fa/reflectometer_fpga_project
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chore: update tb files

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Phil
2026-04-21 19:47:56 +03:00
parent 3dcaaf8ea5
commit 7be26d9d1a
1 changed files with 4 additions and 4 deletions
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8
rtl/accum/tests/Makefile
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@ -8,7 +8,7 @@
# FPGA settings
FPGA_PART = xc7a35tfgg484-1
FPGA_TOP = control
FPGA_TOP = accum
FPGA_ARCH = artix7
RTL_DIR = ../src
@ -21,10 +21,10 @@ SYN_FILES += $(sort $(shell find ../src -type f \( -name '*.v' -o -name '*.sv' \
XCI_FILES = $(sort $(shell find ../src -type f -name '*.xci'))
XDC_FILES += ../../../constraints/ax7a035b.xdc
# XDC_FILES += test_timing.xdc
XDC_FILES += test_timing.xdc
# SYN_FILES += controller_tb.sv
# SIM_TOP = control_tb
SYN_FILES += out_axis_fifo_tb.sv
SIM_TOP = control_tb
program: $(PROJECT).bit