From 7bd1aa68dadbb2f683b21fff23c0a15d0d4f2f87 Mon Sep 17 00:00:00 2001 From: otroubi Date: Fri, 10 Jul 2026 14:03:07 +0300 Subject: [PATCH] add window_sizereg and cfg_bus_valid_reg --- .../src/axi4l_reg_map_controller_pkg.sv | 1 + rtl/controller/src/controller_wrapper_axil.sv | 24 +++++++++---------- 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv index 50d1145..cb4bd1d 100644 --- a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv +++ b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv @@ -45,6 +45,7 @@ AXI write descriptor input and AXI write descriptor status output configuration REG_BIT_W1S, REG_BIT_W1S, REG_BIT_W1S, + REG_BIT_W1S, default: REG_BIT_RSVD }, diff --git a/rtl/controller/src/controller_wrapper_axil.sv b/rtl/controller/src/controller_wrapper_axil.sv index 70e893a..3599a99 100644 --- a/rtl/controller/src/controller_wrapper_axil.sv +++ b/rtl/controller/src/controller_wrapper_axil.sv @@ -1,7 +1,7 @@ module controller_wrapper_axil #( parameter int unsigned DAC_DATA_WIDTH = 12, - parameter int unsigned ADDR_W = 16 - parameter int unsigned DATA_W = 32 + parameter int unsigned ADDR_W = 16, + parameter int unsigned DATA_W = 32, parameter int unsigned USER_W = 1 ) ( @@ -13,7 +13,7 @@ module controller_wrapper_axil #( // adc_clk_in domain input logic finish, - output logic [31:0] window_size, + output logic [31:0] adc_window_size, // dac_clk_in domain outputs output logic [31:0] dac_pulse_width, @@ -32,9 +32,9 @@ module controller_wrapper_axil #( output logic adc_rst ); - logic start, rst_soft, send; - logic [31:0] pulse_width, pulse_period, pulse_num, pulse_height_raw, pulse_period_ADC; - logic [7:0] busy, error_code; + logic start, rst_soft, send, cfg_bus_valid, busy; + logic [31:0] pulse_width, pulse_period, pulse_num, pulse_height_raw, pulse_period_ADC, window_size; + logic [7:0] error_code; logic [31:0] desc_read_addr, desc_read_len, desc_read_config, status_read; logic [31:0] desc_write_addr, desc_write_len_and_tag, status_write_len, status_write_config; @@ -48,6 +48,7 @@ module controller_wrapper_axil #( .s_axil(s_axil), .start_o(start), + .cfg_bus_valid_o(cfg_bus_valid), .send_o(send), .pulse_width_o(pulse_width), .pulse_period_o(pulse_period), @@ -81,10 +82,10 @@ module controller_wrapper_axil #( // [79:64] pulse_num // [95:80] pulse_height_raw[15:0] // [127:96] pulse_period_ADC - // + // [159:128] window_size // ------------------------------------------------------------------------- - (* MARK_DEBUG="true" *) logic [127:0] cfg_bus; - assign cfg_bus = {pulse_period_ADC, pulse_height_raw[15:0], pulse_num[15:0], pulse_period, pulse_width}; + (* MARK_DEBUG="true" *) logic [159:0] cfg_bus; + assign cfg_bus = {window_size, pulse_period_ADC, pulse_height_raw[15:0], pulse_num[15:0], pulse_period, pulse_width}; control #( .DAC_DATA_WIDTH(DAC_DATA_WIDTH) @@ -108,15 +109,12 @@ module controller_wrapper_axil #( .dac_pulse_num(dac_pulse_num), .adc_pulse_period(adc_pulse_period), .adc_pulse_num(adc_pulse_num), + .adc_window_size(adc_window_size), .dac_start(dac_start), .adc_start(adc_start), .dac_rst(dac_rst), .adc_rst(adc_rst) ); - logic [95:0] desc_read; - assign desc_read = {desc_read_config, desc_read_len, desc_read_addr}; - logic [95:0] desc_write; - assign desc_write = {}; endmodule \ No newline at end of file