fix: post-implementation timing sim TB passed

2026-06-23 17:27:20 +03:00
parent b38a693676
commit 771225cd77
3 changed files with 18 additions and 13 deletions
--- a/designs/adc_dac_synchoronizer/sync_top.sv
+++ b/designs/adc_dac_synchoronizer/sync_top.sv
@ -42,8 +42,8 @@ module sync_top
        else if (ADC_DATA_WIDTH < DAC_DATA_WIDTH) begin : g_truncate
            // ЦАП шире АЦП (например, 14 -> 12): забираем младшие биты
            assign internal_wire_signal = dac_signal[DAC_DATA_WIDTH-1:DAC_DATA_WIDTH-ADC_DATA_WIDTH];
-            (* dont_touch = "true" *) wire dummy;
-            assign dummy = ^dac_signal;
+//            (* mark_debug = "true" *) wire dummy;
+//            assign dummy = ^dac_signal;
        end
        else begin : g_match
            // Разрядности равны