baulin.fa/reflectometer_fpga_project
2
0
Fork 0
Code Issues 4 Pull Requests Actions Packages Projects Releases Wiki Activity

fix: post-implementation timing sim TB passed

Browse Source
This commit is contained in:
babintsev.lv
2026-06-23 17:27:20 +03:00
parent b38a693676
commit 771225cd77
3 changed files with 18 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
designs/adc_dac_synchoronizer/debug.xdc
View File

@ -6,7 +6,7 @@ set_clock_groups -asynchronous -group [get_clocks geneartor_clk] -group [get_clo
# set_false_path -through [get_nets -hierarchical {*dac_signal* *internal_wire_singnal* *adc_singnal*}]
# set_false_path -through [get_nets {dac_done dac_done_stretched dac_request adc_done adc_request}]
# set_property DONT_TOUCH true [get_cells -hierarchical -filter {NAME =~ *generator_inst*pulse_height_reg*}]
# set_property DONT_TOUCH true [get_cells -hierarchical -filter {NAME =~ *generator_inst*dac_out_reg*}]
set_property DONT_TOUCH true [get_cells -hierarchical -filter {NAME =~ *generator_inst*pulse_height_reg*}]
set_property DONT_TOUCH true [get_cells -hierarchical -filter {NAME =~ *generator_inst*dac_out_reg*}]
# Применяем к самому проводу сигнала CE, чтобы Vivado не дробила его
# set_property DONT_TOUCH true [get_nets -of_objects [get_pins -hierarchical -filter {PIN_NAME =~ *CE} -of_objects [get_cells *pulse_height_reg*]]]