clk_wiz_libs files fo questa

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/clk_wiz_0.v

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+
+// file: clk_wiz_0.v
+// 
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+//----------------------------------------------------------------------------
+// clk_adc_65__65.00000______0.000______50.0______137.256____148.044
+// clk_adc_65_180__65.00000______0.000______50.0______137.256____148.044
+// clk_dac_125__124.09091______0.000______50.0______123.850____148.044
+// clk_dac_125_180__124.09091______0.000______50.0______123.850____148.044
+//
+//----------------------------------------------------------------------------
+// Input Clock   Freq (MHz)    Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________200.000____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_9_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=5.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
+
+module clk_wiz_0 
+ (
+  // Clock out ports
+  output        clk_adc_65,
+  output        clk_adc_65_180,
+  output        clk_dac_125,
+  output        clk_dac_125_180,
+  // Status and control signals
+  input         reset,
+  output        locked,
+ // Clock in ports
+  input         clk_200
+ );
+
+  clk_wiz_0_clk_wiz inst
+  (
+  // Clock out ports  
+  .clk_adc_65(clk_adc_65),
+  .clk_adc_65_180(clk_adc_65_180),
+  .clk_dac_125(clk_dac_125),
+  .clk_dac_125_180(clk_dac_125_180),
+  // Status and control signals               
+  .reset(reset), 
+  .locked(locked),
+ // Clock in ports
+  .clk_200(clk_200)
+  );
+
+endmodule

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/clk_wiz_0.veo

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+
+// 
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+//----------------------------------------------------------------------------
+// clk_adc_65__65.00000______0.000______50.0______137.256____148.044
+// clk_adc_65_180__65.00000______0.000______50.0______137.256____148.044
+// clk_dac_125__124.09091______0.000______50.0______123.850____148.044
+// clk_dac_125_180__124.09091______0.000______50.0______123.850____148.044
+//
+//----------------------------------------------------------------------------
+// Input Clock   Freq (MHz)    Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________200.000____________0.010
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+  clk_wiz_0 instance_name
+   (
+    // Clock out ports
+    .clk_adc_65(clk_adc_65),     // output clk_adc_65
+    .clk_adc_65_180(clk_adc_65_180),     // output clk_adc_65_180
+    .clk_dac_125(clk_dac_125),     // output clk_dac_125
+    .clk_dac_125_180(clk_dac_125_180),     // output clk_dac_125_180
+    // Status and control signals
+    .reset(reset), // input reset
+    .locked(locked),       // output locked
+   // Clock in ports
+    .clk_200(clk_200));      // input clk_200
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/clk_wiz_0.xdc

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+
+# file: clk_wiz_0.xdc
+# 
+# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system. If required
+# commented constraints can be used in the top level xdc 
+#----------------------------------------------------------------
+# Connect to input port when clock capable pin is selected for input
+create_clock -period 5.000 [get_ports clk_200]
+set_input_jitter [get_clocks -of_objects [get_ports clk_200]] 0.050
+
+
+set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/clk_wiz_0_clk_wiz.v

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+
+// file: clk_wiz_0.v
+// 
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+//----------------------------------------------------------------------------
+// clk_adc_65__65.00000______0.000______50.0______137.256____148.044
+// clk_adc_65_180__65.00000______0.000______50.0______137.256____148.044
+// clk_dac_125__124.09091______0.000______50.0______123.850____148.044
+// clk_dac_125_180__124.09091______0.000______50.0______123.850____148.044
+//
+//----------------------------------------------------------------------------
+// Input Clock   Freq (MHz)    Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________200.000____________0.010
+
+`timescale 1ps/1ps
+
+module clk_wiz_0_clk_wiz 
+
+ (// Clock in ports
+  // Clock out ports
+  output        clk_adc_65,
+  output        clk_adc_65_180,
+  output        clk_dac_125,
+  output        clk_dac_125_180,
+  // Status and control signals
+  input         reset,
+  output        locked,
+  input         clk_200
+ );
+  // Input buffering
+  //------------------------------------
+wire clk_200_clk_wiz_0;
+wire clk_in2_clk_wiz_0;
+  IBUF clkin1_ibufg
+   (.O (clk_200_clk_wiz_0),
+    .I (clk_200));
+
+
+
+
+  // Clocking PRIMITIVE
+  //------------------------------------
+
+  // Instantiation of the MMCM PRIMITIVE
+  //    * Unused inputs are tied off
+  //    * Unused outputs are labeled unused
+
+  wire        clk_adc_65_clk_wiz_0;
+  wire        clk_adc_65_180_clk_wiz_0;
+  wire        clk_dac_125_clk_wiz_0;
+  wire        clk_dac_125_180_clk_wiz_0;
+  wire        clk_out5_clk_wiz_0;
+  wire        clk_out6_clk_wiz_0;
+  wire        clk_out7_clk_wiz_0;
+
+  wire [15:0] do_unused;
+  wire        drdy_unused;
+  wire        psdone_unused;
+  wire        locked_int;
+  wire        clkfbout_clk_wiz_0;
+  wire        clkfbout_buf_clk_wiz_0;
+  wire        clkfboutb_unused;
+    wire clkout0b_unused;
+   wire clkout1b_unused;
+   wire clkout2b_unused;
+   wire clkout3b_unused;
+   wire clkout4_unused;
+  wire        clkout5_unused;
+  wire        clkout6_unused;
+  wire        clkfbstopped_unused;
+  wire        clkinstopped_unused;
+  wire        reset_high;
+
+  MMCME2_ADV
+  #(.BANDWIDTH            ("OPTIMIZED"),
+    .CLKOUT4_CASCADE      ("FALSE"),
+    .COMPENSATION         ("ZHOLD"),
+    .STARTUP_WAIT         ("FALSE"),
+    .DIVCLK_DIVIDE        (5),
+    .CLKFBOUT_MULT_F      (34.125),
+    .CLKFBOUT_PHASE       (0.000),
+    .CLKFBOUT_USE_FINE_PS ("FALSE"),
+    .CLKOUT0_DIVIDE_F     (21.000),
+    .CLKOUT0_PHASE        (0.000),
+    .CLKOUT0_DUTY_CYCLE   (0.500),
+    .CLKOUT0_USE_FINE_PS  ("FALSE"),
+    .CLKOUT1_DIVIDE       (21),
+    .CLKOUT1_PHASE        (0.000),
+    .CLKOUT1_DUTY_CYCLE   (0.500),
+    .CLKOUT1_USE_FINE_PS  ("FALSE"),
+    .CLKOUT2_DIVIDE       (11),
+    .CLKOUT2_PHASE        (0.000),
+    .CLKOUT2_DUTY_CYCLE   (0.500),
+    .CLKOUT2_USE_FINE_PS  ("FALSE"),
+    .CLKOUT3_DIVIDE       (11),
+    .CLKOUT3_PHASE        (0.000),
+    .CLKOUT3_DUTY_CYCLE   (0.500),
+    .CLKOUT3_USE_FINE_PS  ("FALSE"),
+    .CLKIN1_PERIOD        (5.000))
+  mmcm_adv_inst
+    // Output clocks
+   (
+    .CLKFBOUT            (clkfbout_clk_wiz_0),
+    .CLKFBOUTB           (clkfboutb_unused),
+    .CLKOUT0             (clk_adc_65_clk_wiz_0),
+    .CLKOUT0B            (clkout0b_unused),
+    .CLKOUT1             (clk_adc_65_180_clk_wiz_0),
+    .CLKOUT1B            (clkout1b_unused),
+    .CLKOUT2             (clk_dac_125_clk_wiz_0),
+    .CLKOUT2B            (clkout2b_unused),
+    .CLKOUT3             (clk_dac_125_180_clk_wiz_0),
+    .CLKOUT3B            (clkout3b_unused),
+    .CLKOUT4             (clkout4_unused),
+    .CLKOUT5             (clkout5_unused),
+    .CLKOUT6             (clkout6_unused),
+     // Input clock control
+    .CLKFBIN             (clkfbout_buf_clk_wiz_0),
+    .CLKIN1              (clk_200_clk_wiz_0),
+    .CLKIN2              (1'b0),
+     // Tied to always select the primary input clock
+    .CLKINSEL            (1'b1),
+    // Ports for dynamic reconfiguration
+    .DADDR               (7'h0),
+    .DCLK                (1'b0),
+    .DEN                 (1'b0),
+    .DI                  (16'h0),
+    .DO                  (do_unused),
+    .DRDY                (drdy_unused),
+    .DWE                 (1'b0),
+    // Ports for dynamic phase shift
+    .PSCLK               (1'b0),
+    .PSEN                (1'b0),
+    .PSINCDEC            (1'b0),
+    .PSDONE              (psdone_unused),
+    // Other control and status signals
+    .LOCKED              (locked_int),
+    .CLKINSTOPPED        (clkinstopped_unused),
+    .CLKFBSTOPPED        (clkfbstopped_unused),
+    .PWRDWN              (1'b0),
+    .RST                 (reset_high));
+  assign reset_high = reset; 
+
+  assign locked = locked_int;
+// Clock Monitor clock assigning
+//--------------------------------------
+ // Output buffering
+  //-----------------------------------
+
+  BUFG clkf_buf
+   (.O (clkfbout_buf_clk_wiz_0),
+    .I (clkfbout_clk_wiz_0));
+
+
+
+
+
+
+  BUFG clkout1_buf
+   (.O   (clk_adc_65),
+    .I   (clk_adc_65_clk_wiz_0));
+
+
+  BUFG clkout2_buf
+   (.O   (clk_adc_65_180),
+    .I   (clk_adc_65_180_clk_wiz_0));
+
+  BUFG clkout3_buf
+   (.O   (clk_dac_125),
+    .I   (clk_dac_125_clk_wiz_0));
+
+  BUFG clkout4_buf
+   (.O   (clk_dac_125_180),
+    .I   (clk_dac_125_180_clk_wiz_0));
+
+
+
+endmodule

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/clk_wiz_0_ooc.xdc

@@ -0,0 +1,58 @@
+
+# file: clk_wiz_0_ooc.xdc
+# 
+# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#################
+#DEFAULT CLOCK CONSTRAINTS
+
+############################################################
+# Clock Period Constraints                                 #
+############################################################
+#create_clock -period 5.000 [get_ports clk_200]
+

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/clk_wiz_0_sim_netlist.v

@@ -0,0 +1,290 @@
+// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+// Date        : Fri Aug 28 14:05:07 2026
+// Host        : DESKTOP-K2G9PES running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               c:/Users/ASUS/FIZTEX/project/dma_process/dma_process.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
+// Design      : clk_wiz_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7a100tfgg484-2
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* NotValidForBitStream *)
+module clk_wiz_0
+   (clk_adc_65,
+    clk_adc_65_180,
+    clk_dac_125,
+    clk_dac_125_180,
+    reset,
+    locked,
+    clk_200);
+  output clk_adc_65;
+  output clk_adc_65_180;
+  output clk_dac_125;
+  output clk_dac_125_180;
+  input reset;
+  output locked;
+  input clk_200;
+
+  (* IBUF_LOW_PWR *) wire clk_200;
+  wire clk_adc_65;
+  wire clk_adc_65_180;
+  wire clk_dac_125;
+  wire clk_dac_125_180;
+  wire locked;
+  wire reset;
+
+  clk_wiz_0_clk_wiz inst
+       (.clk_200(clk_200),
+        .clk_adc_65(clk_adc_65),
+        .clk_adc_65_180(clk_adc_65_180),
+        .clk_dac_125(clk_dac_125),
+        .clk_dac_125_180(clk_dac_125_180),
+        .locked(locked),
+        .reset(reset));
+endmodule
+
+module clk_wiz_0_clk_wiz
+   (clk_adc_65,
+    clk_adc_65_180,
+    clk_dac_125,
+    clk_dac_125_180,
+    reset,
+    locked,
+    clk_200);
+  output clk_adc_65;
+  output clk_adc_65_180;
+  output clk_dac_125;
+  output clk_dac_125_180;
+  input reset;
+  output locked;
+  input clk_200;
+
+  wire clk_200;
+  wire clk_200_clk_wiz_0;
+  wire clk_adc_65;
+  wire clk_adc_65_180;
+  wire clk_adc_65_180_clk_wiz_0;
+  wire clk_adc_65_clk_wiz_0;
+  wire clk_dac_125;
+  wire clk_dac_125_180;
+  wire clk_dac_125_180_clk_wiz_0;
+  wire clk_dac_125_clk_wiz_0;
+  wire clkfbout_buf_clk_wiz_0;
+  wire clkfbout_clk_wiz_0;
+  wire locked;
+  wire reset;
+  wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
+  wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
+  wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
+  wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
+  wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
+  wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
+  wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
+  wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
+  wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
+  wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
+  wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
+  wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
+  wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
+
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkf_buf
+       (.I(clkfbout_clk_wiz_0),
+        .O(clkfbout_buf_clk_wiz_0));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  (* CAPACITANCE = "DONT_CARE" *) 
+  (* IBUF_DELAY_VALUE = "0" *) 
+  (* IFD_DELAY_VALUE = "AUTO" *) 
+  IBUF #(
+    .IOSTANDARD("DEFAULT")) 
+    clkin1_ibufg
+       (.I(clk_200),
+        .O(clk_200_clk_wiz_0));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkout1_buf
+       (.I(clk_adc_65_clk_wiz_0),
+        .O(clk_adc_65));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkout2_buf
+       (.I(clk_adc_65_180_clk_wiz_0),
+        .O(clk_adc_65_180));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkout3_buf
+       (.I(clk_dac_125_clk_wiz_0),
+        .O(clk_dac_125));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkout4_buf
+       (.I(clk_dac_125_180_clk_wiz_0),
+        .O(clk_dac_125_180));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  MMCME2_ADV #(
+    .BANDWIDTH("OPTIMIZED"),
+    .CLKFBOUT_MULT_F(34.125000),
+    .CLKFBOUT_PHASE(0.000000),
+    .CLKFBOUT_USE_FINE_PS("FALSE"),
+    .CLKIN1_PERIOD(5.000000),
+    .CLKIN2_PERIOD(0.000000),
+    .CLKOUT0_DIVIDE_F(21.000000),
+    .CLKOUT0_DUTY_CYCLE(0.500000),
+    .CLKOUT0_PHASE(0.000000),
+    .CLKOUT0_USE_FINE_PS("FALSE"),
+    .CLKOUT1_DIVIDE(21),
+    .CLKOUT1_DUTY_CYCLE(0.500000),
+    .CLKOUT1_PHASE(0.000000),
+    .CLKOUT1_USE_FINE_PS("FALSE"),
+    .CLKOUT2_DIVIDE(11),
+    .CLKOUT2_DUTY_CYCLE(0.500000),
+    .CLKOUT2_PHASE(0.000000),
+    .CLKOUT2_USE_FINE_PS("FALSE"),
+    .CLKOUT3_DIVIDE(11),
+    .CLKOUT3_DUTY_CYCLE(0.500000),
+    .CLKOUT3_PHASE(0.000000),
+    .CLKOUT3_USE_FINE_PS("FALSE"),
+    .CLKOUT4_CASCADE("FALSE"),
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.500000),
+    .CLKOUT4_PHASE(0.000000),
+    .CLKOUT4_USE_FINE_PS("FALSE"),
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.500000),
+    .CLKOUT5_PHASE(0.000000),
+    .CLKOUT5_USE_FINE_PS("FALSE"),
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.500000),
+    .CLKOUT6_PHASE(0.000000),
+    .CLKOUT6_USE_FINE_PS("FALSE"),
+    .COMPENSATION("ZHOLD"),
+    .DIVCLK_DIVIDE(5),
+    .IS_CLKINSEL_INVERTED(1'b0),
+    .IS_PSEN_INVERTED(1'b0),
+    .IS_PSINCDEC_INVERTED(1'b0),
+    .IS_PWRDWN_INVERTED(1'b0),
+    .IS_RST_INVERTED(1'b0),
+    .REF_JITTER1(0.010000),
+    .REF_JITTER2(0.010000),
+    .SS_EN("FALSE"),
+    .SS_MODE("CENTER_HIGH"),
+    .SS_MOD_PERIOD(10000),
+    .STARTUP_WAIT("FALSE")) 
+    mmcm_adv_inst
+       (.CLKFBIN(clkfbout_buf_clk_wiz_0),
+        .CLKFBOUT(clkfbout_clk_wiz_0),
+        .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
+        .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
+        .CLKIN1(clk_200_clk_wiz_0),
+        .CLKIN2(1'b0),
+        .CLKINSEL(1'b1),
+        .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
+        .CLKOUT0(clk_adc_65_clk_wiz_0),
+        .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
+        .CLKOUT1(clk_adc_65_180_clk_wiz_0),
+        .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
+        .CLKOUT2(clk_dac_125_clk_wiz_0),
+        .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
+        .CLKOUT3(clk_dac_125_180_clk_wiz_0),
+        .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
+        .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
+        .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
+        .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
+        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DCLK(1'b0),
+        .DEN(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
+        .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
+        .DWE(1'b0),
+        .LOCKED(locked),
+        .PSCLK(1'b0),
+        .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
+        .PSEN(1'b0),
+        .PSINCDEC(1'b0),
+        .PWRDWN(1'b0),
+        .RST(reset));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl

@@ -0,0 +1,215 @@
+-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+-- Date        : Fri Aug 28 14:05:07 2026
+-- Host        : DESKTOP-K2G9PES running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode funcsim
+--               c:/Users/ASUS/FIZTEX/project/dma_process/dma_process.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
+-- Design      : clk_wiz_0
+-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+--               synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device      : xc7a100tfgg484-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity clk_wiz_0_clk_wiz is
+  port (
+    clk_adc_65 : out STD_LOGIC;
+    clk_adc_65_180 : out STD_LOGIC;
+    clk_dac_125 : out STD_LOGIC;
+    clk_dac_125_180 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_200 : in STD_LOGIC
+  );
+end clk_wiz_0_clk_wiz;
+
+architecture STRUCTURE of clk_wiz_0_clk_wiz is
+  signal clk_200_clk_wiz_0 : STD_LOGIC;
+  signal clk_adc_65_180_clk_wiz_0 : STD_LOGIC;
+  signal clk_adc_65_clk_wiz_0 : STD_LOGIC;
+  signal clk_dac_125_180_clk_wiz_0 : STD_LOGIC;
+  signal clk_dac_125_clk_wiz_0 : STD_LOGIC;
+  signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
+  signal clkfbout_clk_wiz_0 : STD_LOGIC;
+  signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
+  signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
+  signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
+  signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
+  signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
+  signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
+  signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
+  signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+  signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+  signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
+  signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+  signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
+  signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+  attribute BOX_TYPE : string;
+  attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+  attribute CAPACITANCE : string;
+  attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+  attribute IBUF_DELAY_VALUE : string;
+  attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+  attribute IFD_DELAY_VALUE : string;
+  attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+  attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of clkout4_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clkfbout_clk_wiz_0,
+      O => clkfbout_buf_clk_wiz_0
+    );
+clkin1_ibufg: unisim.vcomponents.IBUF
+    generic map(
+      IOSTANDARD => "DEFAULT"
+    )
+        port map (
+      I => clk_200,
+      O => clk_200_clk_wiz_0
+    );
+clkout1_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clk_adc_65_clk_wiz_0,
+      O => clk_adc_65
+    );
+clkout2_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clk_adc_65_180_clk_wiz_0,
+      O => clk_adc_65_180
+    );
+clkout3_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clk_dac_125_clk_wiz_0,
+      O => clk_dac_125
+    );
+clkout4_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clk_dac_125_180_clk_wiz_0,
+      O => clk_dac_125_180
+    );
+mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
+    generic map(
+      BANDWIDTH => "OPTIMIZED",
+      CLKFBOUT_MULT_F => 34.125000,
+      CLKFBOUT_PHASE => 0.000000,
+      CLKFBOUT_USE_FINE_PS => false,
+      CLKIN1_PERIOD => 5.000000,
+      CLKIN2_PERIOD => 0.000000,
+      CLKOUT0_DIVIDE_F => 21.000000,
+      CLKOUT0_DUTY_CYCLE => 0.500000,
+      CLKOUT0_PHASE => 0.000000,
+      CLKOUT0_USE_FINE_PS => false,
+      CLKOUT1_DIVIDE => 21,
+      CLKOUT1_DUTY_CYCLE => 0.500000,
+      CLKOUT1_PHASE => 0.000000,
+      CLKOUT1_USE_FINE_PS => false,
+      CLKOUT2_DIVIDE => 11,
+      CLKOUT2_DUTY_CYCLE => 0.500000,
+      CLKOUT2_PHASE => 0.000000,
+      CLKOUT2_USE_FINE_PS => false,
+      CLKOUT3_DIVIDE => 11,
+      CLKOUT3_DUTY_CYCLE => 0.500000,
+      CLKOUT3_PHASE => 0.000000,
+      CLKOUT3_USE_FINE_PS => false,
+      CLKOUT4_CASCADE => false,
+      CLKOUT4_DIVIDE => 1,
+      CLKOUT4_DUTY_CYCLE => 0.500000,
+      CLKOUT4_PHASE => 0.000000,
+      CLKOUT4_USE_FINE_PS => false,
+      CLKOUT5_DIVIDE => 1,
+      CLKOUT5_DUTY_CYCLE => 0.500000,
+      CLKOUT5_PHASE => 0.000000,
+      CLKOUT5_USE_FINE_PS => false,
+      CLKOUT6_DIVIDE => 1,
+      CLKOUT6_DUTY_CYCLE => 0.500000,
+      CLKOUT6_PHASE => 0.000000,
+      CLKOUT6_USE_FINE_PS => false,
+      COMPENSATION => "ZHOLD",
+      DIVCLK_DIVIDE => 5,
+      IS_CLKINSEL_INVERTED => '0',
+      IS_PSEN_INVERTED => '0',
+      IS_PSINCDEC_INVERTED => '0',
+      IS_PWRDWN_INVERTED => '0',
+      IS_RST_INVERTED => '0',
+      REF_JITTER1 => 0.010000,
+      REF_JITTER2 => 0.010000,
+      SS_EN => "FALSE",
+      SS_MODE => "CENTER_HIGH",
+      SS_MOD_PERIOD => 10000,
+      STARTUP_WAIT => false
+    )
+        port map (
+      CLKFBIN => clkfbout_buf_clk_wiz_0,
+      CLKFBOUT => clkfbout_clk_wiz_0,
+      CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
+      CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
+      CLKIN1 => clk_200_clk_wiz_0,
+      CLKIN2 => '0',
+      CLKINSEL => '1',
+      CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
+      CLKOUT0 => clk_adc_65_clk_wiz_0,
+      CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
+      CLKOUT1 => clk_adc_65_180_clk_wiz_0,
+      CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
+      CLKOUT2 => clk_dac_125_clk_wiz_0,
+      CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
+      CLKOUT3 => clk_dac_125_180_clk_wiz_0,
+      CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
+      CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
+      CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
+      CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
+      DADDR(6 downto 0) => B"0000000",
+      DCLK => '0',
+      DEN => '0',
+      DI(15 downto 0) => B"0000000000000000",
+      DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
+      DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
+      DWE => '0',
+      LOCKED => locked,
+      PSCLK => '0',
+      PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
+      PSEN => '0',
+      PSINCDEC => '0',
+      PWRDWN => '0',
+      RST => reset
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity clk_wiz_0 is
+  port (
+    clk_adc_65 : out STD_LOGIC;
+    clk_adc_65_180 : out STD_LOGIC;
+    clk_dac_125 : out STD_LOGIC;
+    clk_dac_125_180 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_200 : in STD_LOGIC
+  );
+  attribute NotValidForBitStream : boolean;
+  attribute NotValidForBitStream of clk_wiz_0 : entity is true;
+end clk_wiz_0;
+
+architecture STRUCTURE of clk_wiz_0 is
+begin
+inst: entity work.clk_wiz_0_clk_wiz
+     port map (
+      clk_200 => clk_200,
+      clk_adc_65 => clk_adc_65,
+      clk_adc_65_180 => clk_adc_65_180,
+      clk_dac_125 => clk_dac_125,
+      clk_dac_125_180 => clk_dac_125_180,
+      locked => locked,
+      reset => reset
+    );
+end STRUCTURE;

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/clk_wiz_0_stub.v

@@ -0,0 +1,26 @@
+// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+// Date        : Fri Aug 28 14:05:07 2026
+// Host        : DESKTOP-K2G9PES running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               c:/Users/ASUS/FIZTEX/project/dma_process/dma_process.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
+// Design      : clk_wiz_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7a100tfgg484-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module clk_wiz_0(clk_adc_65, clk_adc_65_180, clk_dac_125, 
+  clk_dac_125_180, reset, locked, clk_200)
+/* synthesis syn_black_box black_box_pad_pin="clk_adc_65,clk_adc_65_180,clk_dac_125,clk_dac_125_180,reset,locked,clk_200" */;
+  output clk_adc_65;
+  output clk_adc_65_180;
+  output clk_dac_125;
+  output clk_dac_125_180;
+  input reset;
+  output locked;
+  input clk_200;
+endmodule

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/clk_wiz_0_stub.vhdl

@@ -0,0 +1,34 @@
+-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
+-- Date        : Fri Aug 28 14:05:07 2026
+-- Host        : DESKTOP-K2G9PES running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub
+--               c:/Users/ASUS/FIZTEX/project/dma_process/dma_process.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+-- Design      : clk_wiz_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7a100tfgg484-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity clk_wiz_0 is
+  Port ( 
+    clk_adc_65 : out STD_LOGIC;
+    clk_adc_65_180 : out STD_LOGIC;
+    clk_dac_125 : out STD_LOGIC;
+    clk_dac_125_180 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_200 : in STD_LOGIC
+  );
+
+end clk_wiz_0;
+
+architecture stub of clk_wiz_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_adc_65,clk_adc_65_180,clk_dac_125,clk_dac_125_180,reset,locked,clk_200";
+begin
+end;

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt

@@ -0,0 +1,260 @@
+2021.2:
+ * Version 6.0 (Rev. 9)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2021.1.1:
+ * Version 6.0 (Rev. 8)
+ * No changes
+
+2021.1:
+ * Version 6.0 (Rev. 8)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.3:
+ * Version 6.0 (Rev. 7)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.2.2:
+ * Version 6.0 (Rev. 6)
+ * No changes
+
+2020.2.1:
+ * Version 6.0 (Rev. 6)
+ * No changes
+
+2020.2:
+ * Version 6.0 (Rev. 6)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.1.1:
+ * Version 6.0 (Rev. 5)
+ * No changes
+
+2020.1:
+ * Version 6.0 (Rev. 5)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2019.2.2:
+ * Version 6.0 (Rev. 4)
+ * No changes
+
+2019.2.1:
+ * Version 6.0 (Rev. 4)
+ * No changes
+
+2019.2:
+ * Version 6.0 (Rev. 4)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2019.1.3:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1.2:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1.1:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1:
+ * Version 6.0 (Rev. 3)
+ * Bug Fix: Internal GUI fixes
+ * Other: New family support added
+
+2018.3.1:
+ * Version 6.0 (Rev. 2)
+ * No changes
+
+2018.3:
+ * Version 6.0 (Rev. 2)
+ * Bug Fix: Made input source independent for primary and secondary clock
+ * Other: New family support added
+
+2018.2:
+ * Version 6.0 (Rev. 1)
+ * Bug Fix: Removed vco freq check when Primitive is None
+ * Other: New family support added
+
+2018.1:
+ * Version 6.0
+ * Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature
+ * Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI
+ * Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals.
+ * Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support
+ * Other: DRCs added for invalid input values in Override mode
+
+2017.4:
+ * Version 5.4 (Rev. 3)
+ * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL
+ * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4
+
+2017.3:
+ * Version 5.4 (Rev. 2)
+ * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices
+
+2017.2:
+ * Version 5.4 (Rev. 1)
+ * General: Internal GUI changes. No effect on the customer design.
+
+2017.1:
+ * Version 5.4
+ * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices.
+ * Other: Added support for new zynq ultrascale plus devices.
+
+2016.4:
+ * Version 5.3 (Rev. 3)
+ * Bug Fix: Internal GUI issues are fixed.
+
+2016.3:
+ * Version 5.3 (Rev. 2)
+ * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs.
+ * Feature Enhancement: Added Matched Routing Option for better timing solutions.
+ * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list.
+ * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
+ * Other: Added support for Spartan7 devices.
+
+2016.2:
+ * Version 5.3 (Rev. 1)
+ * Internal register bit update, no effect on customer designs.
+
+2016.1:
+ * Version 5.3
+ * Added Clock Monitor Feature as part of clocking wizard
+ * DRP registers can be directly written through AXI without resource utilization
+ * Changes to HDL library management to support Vivado IP simulation library
+
+2015.4.2:
+ * Version 5.2 (Rev. 1)
+ * No changes
+
+2015.4.1:
+ * Version 5.2 (Rev. 1)
+ * No changes
+
+2015.4:
+ * Version 5.2 (Rev. 1)
+ * Internal device family change, no functional changes
+
+2015.3:
+ * Version 5.2
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported
+ * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature
+ * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format
+ * Example design and simulation files are delivered in verilog only
+
+2015.2.1:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.2:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.1:
+ * Version 5.1 (Rev. 6)
+ * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices
+ * Supported devices and production status are now determined automatically, to simplify support for future devices
+
+2014.4.1:
+ * Version 5.1 (Rev. 5)
+ * No changes
+
+2014.4:
+ * Version 5.1 (Rev. 5)
+ * Internal device family change, no functional changes
+ * updates related to the source selection based on board interface for zed board
+
+2014.3:
+ * Version 5.1 (Rev. 4)
+ * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface
+
+2014.2:
+ * Version 5.1 (Rev. 3)
+ * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065
+
+2014.1:
+ * Version 5.1 (Rev. 2)
+ * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 5.1 (Rev. 1)
+ * Added support for Ultrascale devices
+ * Updated Board Flow GUI to select the clock interfaces
+ * Fixed issue with Stub file parameter error for BUFR output driver
+
+2013.3:
+ * Version 5.1
+ * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL
+ * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies
+ * Fixed precision issues between displayed and actual frequencies
+ * Added tool tips to GUI
+ * Added Jitter and Phase error values to IP properties
+ * Added support for Cadence IES and Synopsys VCS simulators
+ * Reduced warnings in synthesis and simulation
+ * Enhanced support for IP Integrator
+
+2013.2:
+ * Version 5.0 (Rev. 1)
+ * Fixed issue with clock constraints for multiple instances of clocking wizard
+ * Updated Life-Cycle status of devices
+
+2013.1:
+ * Version 5.0
+ * Lower case ports for Verilog
+ * Added Safe Clock Startup and Clock Sequencing
+
+(c) Copyright 2008 - 2021 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh

@@ -0,0 +1,671 @@
+///////////////////////////////////////////////////////////////////////////////
+//    
+//    Company:          Xilinx
+//    Engineer:         Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
+//    Date:             7/30/2014
+//    Design Name:      MMCME2 DRP
+//    Module Name:      mmcme2_drp_func.h
+//    Version:          1.04
+//    Target Devices:   7 Series || MMCM
+//    Tool versions:    2014.3
+//    Description:      This header provides the functions necessary to  
+//                      calculate the DRP register values for the V6 MMCM.
+//                      
+//	Revision Notes:	3/12 - Updating lookup_low/lookup_high (CR)
+//			4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
+// 
+//    Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
+//                 INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+//                 PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
+//                 PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+//                 ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+//                 APPLICATION OR STANDARD, XILINX IS MAKING NO
+//                 REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+//                 FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+//                 RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+//                 REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
+//                 EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+//                 RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+//                 INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+//                 REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+//                 FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+//                 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+//                 PURPOSE.
+// 
+//                 (c) Copyright 2009-2010 Xilinx, Inc.
+//                 All rights reserved.
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 64
+   );
+   
+   reg [2559:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b01000_01000_1111101000_1111101001_0000000001,
+         40'b01011_01011_1111101000_1111101001_0000000001,
+         40'b01110_01110_1111101000_1111101001_0000000001,
+         40'b10001_10001_1111101000_1111101001_0000000001,
+         40'b10011_10011_1111101000_1111101001_0000000001,
+         40'b10110_10110_1111101000_1111101001_0000000001,
+         40'b11001_11001_1111101000_1111101001_0000000001,
+         40'b11100_11100_1111101000_1111101001_0000000001,
+         40'b11111_11111_1110000100_1111101001_0000000001,
+         40'b11111_11111_1100111001_1111101001_0000000001,
+         40'b11111_11111_1011101110_1111101001_0000000001,
+         40'b11111_11111_1010111100_1111101001_0000000001,
+         40'b11111_11111_1010001010_1111101001_0000000001,
+         40'b11111_11111_1001110001_1111101001_0000000001,
+         40'b11111_11111_1000111111_1111101001_0000000001,
+         40'b11111_11111_1000100110_1111101001_0000000001,
+         40'b11111_11111_1000001101_1111101001_0000000001,
+         40'b11111_11111_0111110100_1111101001_0000000001,
+         40'b11111_11111_0111011011_1111101001_0000000001,
+         40'b11111_11111_0111000010_1111101001_0000000001,
+         40'b11111_11111_0110101001_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0101110111_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+//  and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide, // Max divide is 64
+      input [8*9:0] BANDWIDTH
+   );
+   
+   reg [639:0] lookup_low;
+   reg [639:0] lookup_high;
+   
+   reg [9:0] lookup_entry;
+   
+   begin
+      lookup_low = {
+         // CP_RES_LFHF
+         10'b0010_1111_00,
+         10'b0010_1111_00,
+         10'b0010_1111_00,
+         10'b0010_1111_00,
+         10'b0010_0111_00,
+         10'b0010_1011_00,
+         10'b0010_1101_00,
+         10'b0010_0011_00,
+         10'b0010_0101_00,
+         10'b0010_0101_00,
+         10'b0010_1001_00,
+         10'b0010_1110_00,
+         10'b0010_1110_00,
+         10'b0010_1110_00,
+         10'b0010_1110_00,
+         10'b0010_0001_00,
+         10'b0010_0001_00,
+         10'b0010_0001_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00
+      };
+      
+      lookup_high = {
+         // CP_RES_LFHF
+         10'b0010_1111_00,
+         10'b0100_1111_00,
+         10'b0101_1011_00,
+         10'b0111_0111_00,
+         10'b1101_0111_00,
+         10'b1110_1011_00,
+         10'b1110_1101_00,
+         10'b1111_0011_00,
+         10'b1110_0101_00,
+         10'b1111_0101_00,
+         10'b1111_1001_00,
+         10'b1101_0001_00,
+         10'b1111_1001_00,
+         10'b1111_1001_00,
+         10'b1111_1001_00,
+         10'b1111_1001_00,
+         10'b1111_0101_00,
+         10'b1111_0101_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0111_0001_00,
+         10'b0111_0001_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0110_0001_00,
+         10'b0110_0001_00,
+         10'b0101_0110_00,
+         10'b0101_0110_00,
+         10'b0101_0110_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0100_1010_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      if(BANDWIDTH == "LOW") begin
+         // Low Bandwidth
+         mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+      end else begin
+         // High or optimized bandwidth
+         mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+      end
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 1,000
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
+			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh

@@ -0,0 +1,531 @@
+///////////////////////////////////////////////////////////////////////////////
+//    
+//    Company:          Xilinx
+//    Engineer:         Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
+//    Date:             7/30/2014
+//    Design Name:      PLLE2 DRP
+//    Module Name:      plle2_drp_func.h
+//    Version:          2.00
+//    Target Devices:   7 Series || PLL
+//    Tool versions:    2014.3
+//    Description:      This header provides the functions necessary to  
+//                      calculate the DRP register values for the V6 PLL.
+//                      Updated for CR663854.
+// 
+//    Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
+//                 INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+//                 PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
+//                 PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+//                 ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+//                 APPLICATION OR STANDARD, XILINX IS MAKING NO
+//                 REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+//                 FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+//                 RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+//                 REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
+//                 EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+//                 RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+//                 INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+//                 REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+//                 FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+//                 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+//                 PURPOSE.
+// 
+//                 (c) Copyright 2009-2010 Xilinx, Inc.
+//                 All rights reserved.
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+`ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+`endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+`ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+`endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+`ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+`endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+`ifdef DEBUG
+      $display("temp: %h", temp);
+`endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 64
+   );
+   
+   reg [2559:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b01000_01000_1111101000_1111101001_0000000001,
+         40'b01011_01011_1111101000_1111101001_0000000001,
+         40'b01110_01110_1111101000_1111101001_0000000001,
+         40'b10001_10001_1111101000_1111101001_0000000001,
+         40'b10011_10011_1111101000_1111101001_0000000001,
+         40'b10110_10110_1111101000_1111101001_0000000001,
+         40'b11001_11001_1111101000_1111101001_0000000001,
+         40'b11100_11100_1111101000_1111101001_0000000001,
+         40'b11111_11111_1110000100_1111101001_0000000001,
+         40'b11111_11111_1100111001_1111101001_0000000001,
+         40'b11111_11111_1011101110_1111101001_0000000001,
+         40'b11111_11111_1010111100_1111101001_0000000001,
+         40'b11111_11111_1010001010_1111101001_0000000001,
+         40'b11111_11111_1001110001_1111101001_0000000001,
+         40'b11111_11111_1000111111_1111101001_0000000001,
+         40'b11111_11111_1000100110_1111101001_0000000001,
+         40'b11111_11111_1000001101_1111101001_0000000001,
+         40'b11111_11111_0111110100_1111101001_0000000001,
+         40'b11111_11111_0111011011_1111101001_0000000001,
+         40'b11111_11111_0111000010_1111101001_0000000001,
+         40'b11111_11111_0110101001_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0101110111_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+//  and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide, // Max divide is 64
+      input [8*9:0] BANDWIDTH
+   );
+   
+   reg [639:0] lookup_low;
+   reg [639:0] lookup_high;
+   
+   reg [9:0] lookup_entry;
+   
+   begin
+      lookup_low = {
+         // CP_RES_LFHF
+         10'b0010_1111_00,
+         10'b0010_1111_00,
+         10'b0010_0111_00,
+         10'b0010_1101_00,
+         10'b0010_0101_00,
+         10'b0010_0101_00,
+         10'b0010_1001_00,
+         10'b0010_1110_00,
+         10'b0010_1110_00,
+         10'b0010_0001_00,
+         10'b0010_0001_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00
+      };
+      
+      lookup_high = {
+         // CP_RES_LFHF
+         10'b0011_0111_00,
+         10'b0011_0111_00,
+         10'b0101_1111_00,
+         10'b0111_1111_00,
+         10'b0111_1011_00,
+         10'b1101_0111_00,
+         10'b1110_1011_00,
+         10'b1110_1101_00,
+         10'b1111_1101_00,
+         10'b1111_0111_00,
+         10'b1111_1011_00,
+         10'b1111_1101_00,
+         10'b1111_0011_00,
+         10'b1110_0101_00,
+         10'b1111_0101_00,
+         10'b1111_0101_00,
+         10'b1111_0101_00,
+         10'b1111_0101_00,
+         10'b0111_0110_00,
+         10'b0111_0110_00,
+         10'b0111_0110_00,
+         10'b0111_0110_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b0100_0010_00,
+         10'b0100_0010_00,
+         10'b0100_0010_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0011_0100_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      if(BANDWIDTH == "LOW") begin
+         // Low Bandwidth
+         mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+      end else begin
+         // High or optimized bandwidth
+         mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+      end
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+`endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+`ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+`endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh

@@ -0,0 +1,671 @@
+///////////////////////////////////////////////////////////////////////////////
+//    
+//    Company:          Xilinx
+//    Engineer:         Jim Tatsukawa
+//    Date:             7/30/2014
+//    Design Name:      MMCME2 DRP
+//    Module Name:      mmcme2_drp_func.h
+//    Version:          1.04
+//    Target Devices:   UltraScale Architecture || MMCM 
+//    Tool versions:    2014.3
+//    Description:      This header provides the functions necessary to  
+//                      calculate the DRP register values for the V6 MMCM.
+//                      
+//	Revision Notes:	3/22 - Updating lookup_low/lookup_high (CR)
+//				4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
+// 
+//    Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
+//                 INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+//                 PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
+//                 PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+//                 ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+//                 APPLICATION OR STANDARD, XILINX IS MAKING NO
+//                 REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+//                 FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+//                 RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+//                 REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
+//                 EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+//                 RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+//                 INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+//                 REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+//                 FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+//                 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+//                 PURPOSE.
+// 
+//                 (c) Copyright 2009-2010 Xilinx, Inc.
+//                 All rights reserved.
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 64
+   );
+   
+   reg [2559:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b01000_01000_1111101000_1111101001_0000000001,
+         40'b01011_01011_1111101000_1111101001_0000000001,
+         40'b01110_01110_1111101000_1111101001_0000000001,
+         40'b10001_10001_1111101000_1111101001_0000000001,
+         40'b10011_10011_1111101000_1111101001_0000000001,
+         40'b10110_10110_1111101000_1111101001_0000000001,
+         40'b11001_11001_1111101000_1111101001_0000000001,
+         40'b11100_11100_1111101000_1111101001_0000000001,
+         40'b11111_11111_1110000100_1111101001_0000000001,
+         40'b11111_11111_1100111001_1111101001_0000000001,
+         40'b11111_11111_1011101110_1111101001_0000000001,
+         40'b11111_11111_1010111100_1111101001_0000000001,
+         40'b11111_11111_1010001010_1111101001_0000000001,
+         40'b11111_11111_1001110001_1111101001_0000000001,
+         40'b11111_11111_1000111111_1111101001_0000000001,
+         40'b11111_11111_1000100110_1111101001_0000000001,
+         40'b11111_11111_1000001101_1111101001_0000000001,
+         40'b11111_11111_0111110100_1111101001_0000000001,
+         40'b11111_11111_0111011011_1111101001_0000000001,
+         40'b11111_11111_0111000010_1111101001_0000000001,
+         40'b11111_11111_0110101001_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0101110111_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+//  and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide, // Max divide is 64
+      input [8*9:0] BANDWIDTH
+   );
+   
+   reg [639:0] lookup_low;
+   reg [639:0] lookup_high;
+   
+   reg [9:0] lookup_entry;
+   
+   begin
+      lookup_low = {
+         // CP_RES_LFHF
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_0111_11,
+         10'b0010_0111_11,
+         10'b0010_0111_11,
+         10'b0010_1101_11,
+         10'b0010_1101_11,
+         10'b0010_1101_11,
+         10'b0010_0011_11,
+         10'b0010_0101_11,
+         10'b0010_0101_11,
+         10'b0010_0101_11,
+         10'b0010_1001_11,
+         10'b0010_1001_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_0001_11,
+         10'b0010_0001_11,
+         10'b0010_0001_11,
+         10'b0010_0001_11,
+         10'b0010_0001_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11
+      };
+      
+      lookup_high = {
+         // CP_RES_LFHF
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1011_11,
+         10'b0011_1111_11,
+         10'b0100_1111_11,
+         10'b0100_1111_11,
+         10'b0101_1111_11,
+         10'b0110_1111_11,
+         10'b0111_1111_11,
+         10'b0111_1111_11,
+         10'b1100_1111_11,
+         10'b1101_1111_11,
+         10'b1110_1111_11,
+         10'b1111_1111_11,
+         10'b1111_1111_11,
+         10'b1110_0111_11,
+         10'b1110_1011_11,
+         10'b1111_0111_11,
+         10'b1111_1011_11,
+         10'b1111_1011_11,
+         10'b1110_1101_11,
+         10'b1111_1101_11,
+         10'b1111_1101_11,
+         10'b1111_0011_11,
+         10'b1111_0011_11,
+         10'b1111_0011_11,
+         10'b1110_0101_11,
+         10'b1110_0101_11,
+         10'b1110_0101_11,
+         10'b1111_0101_11,
+         10'b1111_0101_11,
+         10'b1111_0101_11,
+         10'b1111_1001_11,
+         10'b1111_1001_11,
+         10'b1111_1001_11,
+         10'b1111_1001_11,
+         10'b1111_1001_11,
+         10'b1110_1110_11,
+         10'b1110_1110_11,
+         10'b1110_1110_11,
+         10'b1110_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1110_0001_11,
+         10'b1110_0001_11,
+         10'b1110_0001_11,
+         10'b1110_0001_11,
+         10'b1110_0001_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_1010_11,
+         10'b1100_1010_11,
+         10'b1100_1010_11,
+         10'b1100_1010_11
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      if(BANDWIDTH == "LOW") begin
+         // Low Bandwidth
+         mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+      end else begin
+         // High or optimized bandwidth
+         mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+      end
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 1,000
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
+			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh

@@ -0,0 +1,530 @@
+///////////////////////////////////////////////////////////////////////////////
+//    
+//    Company:          Xilinx
+//    Engineer:         Jim Tatsukawa
+//    Date:             6/15/2015
+//    Design Name:      PLLE3 DRP
+//    Module Name:      plle3_drp_func.h
+//    Version:          1.10
+//    Target Devices:   UltraScale Architecture
+//    Tool versions:    2015.1
+//    Description:      This header provides the functions necessary to  
+//                      calculate the DRP register values for the V6 PLL.
+//                      
+//	Revision Notes:	8/11 - PLLE3 updated for PLLE3 file 4564419
+//	Revision Notes:	6/15 - pll_filter_lookup fixed for max M of 19
+//                         PM_Rise bits have been removed for PLLE3
+// 
+//    Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
+//                 INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+//                 PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
+//                 PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+//                 ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+//                 APPLICATION OR STANDARD, XILINX IS MAKING NO
+//                 REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+//                 FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+//                 RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+//                 REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
+//                 EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+//                 RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+//                 INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+//                 REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+//                 FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+//                 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+//                 PURPOSE.
+// 
+//                 (c) Copyright 2009-2010 Xilinx, Inc.
+//                 All rights reserved.
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 64
+   );
+   
+   reg [759:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001, //1  
+         40'b00110_00110_1111101000_1111101001_0000000001, //2
+         40'b01000_01000_1111101000_1111101001_0000000001, //3
+         40'b01011_01011_1111101000_1111101001_0000000001, //4
+         40'b01110_01110_1111101000_1111101001_0000000001, //5
+         40'b10001_10001_1111101000_1111101001_0000000001, //6
+         40'b10011_10011_1111101000_1111101001_0000000001, //7
+         40'b10110_10110_1111101000_1111101001_0000000001, //8
+         40'b11001_11001_1111101000_1111101001_0000000001, //9
+         40'b11100_11100_1111101000_1111101001_0000000001, //10
+         40'b11111_11111_1110000100_1111101001_0000000001, //11
+         40'b11111_11111_1100111001_1111101001_0000000001, //12
+         40'b11111_11111_1011101110_1111101001_0000000001, //13
+         40'b11111_11111_1010111100_1111101001_0000000001, //14
+         40'b11111_11111_1010001010_1111101001_0000000001, //15
+         40'b11111_11111_1001110001_1111101001_0000000001, //16
+         40'b11111_11111_1000111111_1111101001_0000000001, //17
+         40'b11111_11111_1000100110_1111101001_0000000001, //18
+         40'b11111_11111_1000001101_1111101001_0000000001 //19
+         
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+//  and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide // Max divide is 19
+   );
+   
+   reg [639:0] lookup;
+   reg [9:0] lookup_entry;
+   
+   begin
+
+      lookup = {
+         // CP_RES_LFHF
+         10'b0010_1111_01, //1
+         10'b0010_0011_11, //2
+         10'b0011_0011_11, //3
+         10'b0010_0001_11, //4
+         10'b0010_0110_11, //5
+         10'b0010_1010_11, //6
+         10'b0010_1010_11, //7
+         10'b0011_0110_11, //8
+         10'b0010_1100_11, //9
+         10'b0010_1100_11, //10
+         10'b0010_1100_11, //11
+         10'b0010_0010_11, //12
+         10'b0011_1100_11, //13
+         10'b0011_1100_11, //14
+         10'b0011_1100_11, //15
+         10'b0011_1100_11, //16
+         10'b0011_0010_11, //17
+         10'b0011_0010_11, //18
+         10'b0011_0010_11 //19
+      };
+      
+         mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10];
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+   (
+      input [8*9:0] CLKOUTPHY_MODE
+   );
+
+      if(CLKOUTPHY_MODE == "VCO_X2") begin
+         mmcm_pll_clkoutphy_calc= 2'b00;
+      end else if(CLKOUTPHY_MODE == "VCO") begin
+         mmcm_pll_clkoutphy_calc= 2'b01;
+      end else if(CLKOUTPHY_MODE == "CLKIN") begin
+         mmcm_pll_clkoutphy_calc= 2'b11;
+      end else begin // Assume "VCO_HALF"
+         mmcm_pll_clkoutphy_calc= 2'b10;
+      end
+      
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_pll_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 1,000
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_pll_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
+			3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+//			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+
+

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh

@@ -0,0 +1,861 @@
+///////////////////////////////////////////////////////////////////////////////
+//    
+//    Company:          Xilinx
+//    Engineer:         Jim Tatsukawa. Updated by Ralf Krueger
+//    Date:             7/30/2014
+//    Design Name:      MMCME4 DRP
+//    Module Name:      mmcme4_drp_func.h
+//    Version:          1.31
+//    Target Devices:   UltraScale Plus Architecture
+//    Tool versions:    2017.1
+//    Description:      This header provides the functions necessary to  
+//                      calculate the DRP register values for UltraScal+ MMCM.
+//                      
+//	Revision Notes:	3/22 - Updating lookup_low/lookup_high (CR)
+//				4/13 - Fractional divide function in mmcm_frac_count_calc function
+//              2/28/17 - Updated for Ultrascale Plus
+// 
+//    Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
+//                 INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+//                 PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
+//                 PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+//                 ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+//                 APPLICATION OR STANDARD, XILINX IS MAKING NO
+//                 REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+//                 FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+//                 RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+//                 REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
+//                 EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+//                 RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+//                 INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+//                 REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+//                 FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+//                 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+//                 PURPOSE.
+// 
+//                 (c) Copyright 2009-2017 Xilinx, Inc.
+//                 All rights reserved.
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages during elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers.  These should not be modified, they are for development only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+// greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      // of 1 would modify the fractional so that instead of being a .16
+      // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//       is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      // assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_phase-divide:%d,phase:%d", divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [7:0] divide // Max M divide is 128 in UltrascalePlus
+   );
+   
+   reg [5119:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001,      // M=1 (not allowed)
+         40'b00110_00110_1111101000_1111101001_0000000001,      // M=2
+         40'b01000_01000_1111101000_1111101001_0000000001,      // M=3
+         40'b01011_01011_1111101000_1111101001_0000000001,      // M=4
+         40'b01110_01110_1111101000_1111101001_0000000001,      // M=5
+         40'b10001_10001_1111101000_1111101001_0000000001,      // M=6
+         40'b10011_10011_1111101000_1111101001_0000000001,      // M=7
+         40'b10110_10110_1111101000_1111101001_0000000001,
+         40'b11001_11001_1111101000_1111101001_0000000001,
+         40'b11100_11100_1111101000_1111101001_0000000001,
+         40'b11111_11111_1110000100_1111101001_0000000001,
+         40'b11111_11111_1100111001_1111101001_0000000001,
+         40'b11111_11111_1011101110_1111101001_0000000001,
+         40'b11111_11111_1010111100_1111101001_0000000001,
+         40'b11111_11111_1010001010_1111101001_0000000001,
+         40'b11111_11111_1001110001_1111101001_0000000001,
+         40'b11111_11111_1000111111_1111101001_0000000001,
+         40'b11111_11111_1000100110_1111101001_0000000001,
+         40'b11111_11111_1000001101_1111101001_0000000001,
+         40'b11111_11111_0111110100_1111101001_0000000001,
+         40'b11111_11111_0111011011_1111101001_0000000001,
+         40'b11111_11111_0111000010_1111101001_0000000001,
+         40'b11111_11111_0110101001_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0101110111_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,                                                                    
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,                                                                    
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,      // M=127
+         40'b11111_11111_0011111010_1111101001_0000000001       // M=128
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+//  and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [7:0] divide, //  input [7:0] divide // Max M divide is 128 in UltraScalePlus
+      input [8*9:0] BANDWIDTH
+   );
+   
+   reg [1279:0] lookup_low;
+   reg [1279:0] lookup_high;
+   
+   reg [9:0] lookup_entry;
+   
+   begin
+      lookup_low = {
+         // CP_RES_LFHF
+       	10'b0011_1111_11,    // M=1 - not legal
+       	10'b0011_1111_11,    // M=2
+       	10'b0011_1101_11,    // M=3
+       	10'b0011_0101_11,    // M=4
+       	10'b0011_1001_11,    // M=5
+       	10'b0011_1110_11,    // M=6
+       	10'b0011_1110_11,    // M=7
+       	10'b0011_0001_11,
+       	10'b0011_0110_11,
+       	10'b0011_0110_11,
+       	10'b0011_0110_11,
+       	10'b0011_1010_11,
+       	10'b0011_1010_11,
+       	10'b0011_1010_11,
+       	10'b0100_0110_11,
+       	10'b0011_1100_11,
+       	10'b1110_0110_11,
+       	10'b1111_0110_11,
+       	10'b1110_1010_11,
+       	10'b1110_1010_11,
+       	10'b1111_1010_11,
+       	10'b1111_1010_11,
+       	10'b1111_1010_11,
+       	10'b1111_1010_11,
+       	10'b1111_1010_11,
+       	10'b1101_1100_11,
+       	10'b1101_1100_11,
+       	10'b1101_1100_11,
+       	10'b1110_1100_11,
+       	10'b1110_1100_11,
+       	10'b1110_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1110_0010_11,
+       	10'b1110_0010_11,
+       	10'b1110_0010_11,
+       	10'b1110_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11, // M=127
+       	10'b1101_1000_11  // M=128
+};										
+      
+      lookup_high = {
+         // CP_RES_LFHF
+       10'b0111_1111_11,    // M=1 - not legal
+       10'b0111_1111_11,    // M=2
+       10'b1110_1111_11,    // M=3
+       10'b1111_1111_11,    // M=4
+       10'b1111_1011_11,    // M=5
+       10'b1111_1101_11,    // M=6
+       10'b1111_0011_11,    // M=7
+       10'b1110_0101_11,
+       10'b1111_1001_11,
+       10'b1111_1001_11,
+       10'b1110_1110_11,
+       10'b1111_1110_11,
+       10'b1111_0001_11,
+       10'b1111_0001_11,
+       10'b1111_0001_11,
+       10'b1110_0110_11,
+       10'b1110_0110_11,
+       10'b1111_0110_11,
+       10'b1110_1010_11,
+       10'b1110_1010_11,
+       10'b1111_1010_11,
+       10'b1111_1010_11,
+       10'b1111_1010_11,
+       10'b1111_1010_11,
+       10'b1111_1010_11,
+       10'b1101_1100_11,
+       10'b1101_1100_11,
+       10'b1101_1100_11,
+       10'b1110_1100_11,
+       10'b1110_1100_11,
+       10'b1110_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1110_0010_11,
+       10'b1110_0010_11,
+       10'b1110_0010_11,
+       10'b1110_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11     // M=128
+};
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      if(BANDWIDTH == "LOW") begin
+         // Low Bandwidth
+         mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10];
+      end else begin
+         // High or optimized bandwidth
+         mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10];
+      end
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1);   //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);    //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], 
+			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+

designs/full_new_reflectometer/src/clk_ctrl_wiz/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh

@@ -0,0 +1,536 @@
+///////////////////////////////////////////////////////////////////////////////
+//    
+//    Company:          Xilinx
+//    Engineer:         Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ 
+//    Date:             6/15/2015
+//    Design Name:      PLLE4 DRP
+//    Module Name:      plle4_drp_func.h
+//    Version:          2.0
+//    Target Devices:   UltraScale+ Architecture
+//    Tool versions:    2017.1
+//    Description:      This header provides the functions necessary to  
+//                      calculate the DRP register values for the V6 PLL.
+//                      
+//	Revision Notes:	8/11 - PLLE3 updated for PLLE3 file 4564419
+//	Revision Notes:	6/15 - pll_filter_lookup fixed for max M of 19
+//                           M_Rise bits have been removed for PLLE3
+//	Revision Notes:	2/28/17 - pll_filter_lookup and CPRES updated for 
+//                           Ultrascale+ and for max M of 21
+// 
+//    Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
+//                 INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+//                 PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
+//                 PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+//                 ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+//                 APPLICATION OR STANDARD, XILINX IS MAKING NO
+//                 REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+//                 FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+//                 RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+//                 REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
+//                 EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+//                 RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+//                 INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+//                 REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+//                 FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+//                 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+//                 PURPOSE.
+// 
+//                 (c) Copyright 2009-2017 Xilinx, Inc.
+//                 All rights reserved.
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+         $display("ERROR: phase of $phase is not between -360000 and 360000");
+`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 21
+   );
+   
+   reg [839:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+
+         40'b00110_00110_1111101000_1111101001_0000000001, //2
+         40'b01000_01000_1111101000_1111101001_0000000001, //3
+         40'b01011_01011_1111101000_1111101001_0000000001, //4
+         40'b01110_01110_1111101000_1111101001_0000000001, //5
+         40'b10001_10001_1111101000_1111101001_0000000001, //6
+         40'b10011_10011_1111101000_1111101001_0000000001, //7
+         40'b10110_10110_1111101000_1111101001_0000000001, //8
+         40'b11001_11001_1111101000_1111101001_0000000001, //9
+         40'b11100_11100_1111101000_1111101001_0000000001, //10
+         40'b11111_11111_1110000100_1111101001_0000000001, //11
+         40'b11111_11111_1100111001_1111101001_0000000001, //12
+         40'b11111_11111_1011101110_1111101001_0000000001, //13
+         40'b11111_11111_1010111100_1111101001_0000000001, //14
+         40'b11111_11111_1010001010_1111101001_0000000001, //15
+         40'b11111_11111_1001110001_1111101001_0000000001, //16
+         40'b11111_11111_1000111111_1111101001_0000000001, //17
+         40'b11111_11111_1000100110_1111101001_0000000001, //18
+         40'b11111_11111_1000001101_1111101001_0000000001, //19
+         40'b11111_11111_0111110100_1111101001_0000000001, //20
+         40'b11111_11111_0111011011_1111101001_0000000001  //21
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+//  and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide // Max divide is 21
+   );
+   
+   reg [209:0] lookup;
+   reg [9:0] lookup_entry;
+   
+   begin
+
+      lookup = {
+         // CP_RES_LFHF
+         10'b0011_0111_11, //1  not legal in Ultrascale+
+         10'b0011_0111_11, //2
+         10'b0011_0011_11, //3
+         10'b0011_1001_11, //4
+         10'b0011_0001_11, //5
+         10'b0100_1110_11, //6
+         10'b0011_0110_11, //7
+         10'b0011_1010_11, //8
+         10'b0111_1001_11, //9
+         10'b0111_1001_11, //10
+         10'b0101_0110_11, //11
+         10'b1100_0101_11, //12
+         10'b0101_1010_11, //13
+         10'b0110_0110_11, //14
+         10'b0110_1010_11, //15
+         10'b0111_0110_11, //16
+         10'b1111_0101_11, //17
+         10'b1100_0110_11, //18
+         10'b1110_0001_11, //19
+         10'b1101_0110_11, //20
+         10'b1111_0001_11  //21
+      };
+      
+         mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10];
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO" 
+// will need to divide the doubled clock VCO clock frequency by 
+// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will 
+// need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+   (
+      input [8*9:0] CLKOUTPHY_MODE
+   );
+
+      if(CLKOUTPHY_MODE == "VCO_X2") begin
+         mmcm_pll_clkoutphy_calc= 2'b00;
+      end else if(CLKOUTPHY_MODE == "VCO") begin
+         mmcm_pll_clkoutphy_calc= 2'b01;
+      end else if(CLKOUTPHY_MODE == "CLKIN") begin
+         mmcm_pll_clkoutphy_calc= 2'b11;
+      end else begin // Assume "VCO_HALF"
+         mmcm_pll_clkoutphy_calc= 2'b10;
+      end
+      
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_pll_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 1,000
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_pll_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
+			3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+

designs/full_new_reflectometer/tests/full_reflectometer_test/Makefile

@@ -35,7 +35,6 @@ VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller_pkg.sv
 VERILOG_SOURCES += $(RTL_DIR)/axis_defaults_helper.sv
 VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller.sv
 VERILOG_SOURCES += $(RTL_DIR)/axi_dma_wrapper_if.sv
-VERILOG_SOURCES += $(RTL_DIR)/wrapper_controller_dma.sv
 VERILOG_SOURCES += $(RTL_ACCUM_DIR)/adder.sv
 VERILOG_SOURCES += $(RTL_ACCUM_DIR)/out_axis_fifo.sv
 VERILOG_SOURCES += $(RTL_ACCUM_DIR)/accum.sv
@@ -47,8 +46,8 @@ VERILOG_SOURCES += $(RTL_CLK_DIR)/clk_wiz_0.v
 
 VERILOG_SOURCES += $(PWD)/adc_model.sv
 VERILOG_SOURCES += $(PWD)/dac_model.sv
-VERILOG_SOURCES += $(PWD)/reflectometer_ip.sv
+VERILOG_SOURCES += $(RTL_DIR)/reflectometer_ip.sv
-VERILOG_SOURCES += $(PWD)/reflectometer_and_dma_wrapper.sv
+VERILOG_SOURCES += $(RTL_DIR)/reflectometer_and_dma_wrapper.sv
 VERILOG_SOURCES += $(PWD)/tb_full_reflectometer.sv
 VERILOG_SOURCES += /mnt/c/Xilinx/Vivado/2021.2/data/verilog/src/glbl.v
 

designs/full_new_reflectometer/tests/full_reflectometer_test/reflectometer_and_dma_wrapper.sv

@@ -1,177 +0,0 @@
-`timescale 1 ns / 1 ns
-
-module reflectometer_and_dma_wrapper 
-#(
-    // parameters for base reflectometer works
-    parameter int unsigned DAC_DATA_WIDTH = 14,
-    parameter int unsigned ADC_DATA_WIDTH = 12,
-    parameter int unsigned PACK_FACTOR = 1,
-    parameter int unsigned PROCESS_MODE = 0,
-    parameter int unsigned ZERO_LEVEL = 8192,
-    parameter int unsigned ACCUM_WIDTH = 32,
-    parameter int unsigned N_MAX = 4096,
-    parameter int unsigned PACKET_SIZE = 1024,
-    parameter int unsigned RD_FIFO_WIDTH = 32,
-
-    // parameters for DMA and interfaces
-    parameter int unsigned ADDR_W             = 16,
-    parameter int unsigned DATA_W             = 32,
-    parameter int unsigned USER_W             = 1,
-
-    parameter int unsigned AXI_DATA_WIDTH     = 32,
-
-    parameter int unsigned AXI_STRB_WIDTH     = AXI_DATA_WIDTH / 8,
-    parameter int unsigned AXI_USER_WIDTH     = 1,
-    parameter int unsigned AXI_MAX_BURST_LEN  = 16,
-
-    parameter int unsigned AXIS_DATA_WIDTH    = AXI_DATA_WIDTH,
-    parameter int unsigned AXIS_KEEP_ENABLE   = AXIS_DATA_WIDTH > 8,
-    parameter int unsigned AXIS_KEEP_WIDTH    = AXIS_DATA_WIDTH / 8,
-    parameter int unsigned AXIS_LAST_ENABLE   = 1,
-    parameter int unsigned AXIS_ID_ENABLE     = 1,
-    parameter int unsigned AXIS_DEST_ENABLE   = 0,
-    parameter int unsigned AXIS_USER_ENABLE   = 1,
-
-    parameter int unsigned ENABLE_SG          = 0,
-    parameter int unsigned ENABLE_UNALIGNED   = 0,
-
-    parameter int unsigned PIPELINE_OUTPUT    = 0
-)
-(
-    input  logic                       ctrl_clk,
-    input  logic                       rst_n,
-    output  wire                       locked,
-
-    axi4l_if.slave                     s_axil,
-    axi4_if.master                      m_axi,
-    // todo
-    axis_if.master                     m_axis_read_data,
-
-        // DAC
-    output  wire                        dac_clk_o,
-    output  wire [DAC_DATA_WIDTH-1:0]   dac_data,
-    output  wire                        dac_wrt,
-
-    // ADC
-    output  wire                        adc_clk_o,
-    input   wire [ADC_DATA_WIDTH-1:0]   adc_data,
-    input   wire                        adc_otr
-
-
-);
-
-    axis_if #(
-    .DATA_W($bits(dma_read_status_t)),
-    .KEEP_W(($bits(dma_read_status_t)+7)/8),
-    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
-    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
-    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
-  ) s_axis_status_read (
-    .aclk(ctrl_clk),
-    .aresetn(rst_n)
-  );
-
-  axis_if #(
-    .DATA_W($bits(dma_write_status_t)),
-    .KEEP_W(($bits(dma_write_status_t)+7)/8),
-    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
-    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
-    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
-  ) s_axis_status_write (
-    .aclk(ctrl_clk),
-    .aresetn(rst_n)
-  );
-
-  axis_if #(
-    .DATA_W($bits(dma_read_desc_t)),
-    .KEEP_W(($bits(dma_read_desc_t)+7)/8),
-    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
-    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
-    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
-  ) m_axis_desc_read (
-    .aclk(ctrl_clk),
-    .aresetn(rst_n)
-  );
-
-  axis_if #(
-    .DATA_W($bits(dma_write_desc_t)),
-    .KEEP_W(($bits(dma_write_desc_t)+7)/8),
-    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
-    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
-    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
-  ) m_axis_desc_write (
-    .aclk(ctrl_clk),
-    .aresetn(rst_n)
-  );
-
-  axis_if #(
-    .DATA_W(RD_FIFO_WIDTH),
-    .KEEP_W((RD_FIFO_WIDTH+7)/8),
-    .ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
-    .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
-    .USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
-  ) m_axis_accum (
-    .aclk(ctrl_clk),
-    .aresetn(rst_n)
-  );
-
-    reflectometer_top #(
-        .DAC_DATA_WIDTH(DAC_DATA_WIDTH),
-        .ADC_DATA_WIDTH(ADC_DATA_WIDTH),
-        .PACK_FACTOR(PACK_FACTOR),
-        .PROCESS_MODE(PROCESS_MODE),
-        .ZERO_LEVEL(ZERO_LEVEL),
-        .ACCUM_WIDTH(ACCUM_WIDTH),
-        .N_MAX(N_MAX),
-        .PACKET_SIZE(PACKET_SIZE),
-        .RD_FIFO_WIDTH(RD_FIFO_WIDTH)
-    ) reflectometer_top_inst (
-        .ctrl_clk(ctrl_clk),
-        .rst_n(rst_n),
-        .locked(locked),
-        .s_axil(s_axil),
-        .m_axis_accum(m_axis_accum),
-        .s_axis_status_read(s_axis_status_read),
-        .s_axis_status_write(s_axis_status_write),
-        .m_axis_desc_read(m_axis_desc_read),
-        .m_axis_desc_write(m_axis_desc_write),
-
-        .dac_clk_o(dac_clk_o),
-        .dac_data(dac_data),
-        .dac_wrt(dac_wrt),
-        .adc_clk_o(adc_clk_o),
-        .adc_data(adc_data),
-        .adc_otr(adc_otr)
-    );
-
-    //------------------------------------------------------------
-    // DMA
-    //------------------------------------------------------------
-    axi_dma_wrapper #(
-        .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
-        .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
-        .AXI_USER_WIDTH(AXI_USER_WIDTH),
-        .AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
-        .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
-        .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
-        .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
-        .AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
-        .AXIS_ID_ENABLE(AXIS_ID_ENABLE),
-        .AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
-        .AXIS_USER_ENABLE(AXIS_USER_ENABLE),
-        .ENABLE_SG(ENABLE_SG),
-        .ENABLE_UNALIGNED(ENABLE_UNALIGNED)
-    ) axi_dma_wrapper_inst
-    (
-        .clk(ctrl_clk),
-        .rst(!rst_n),
-        .s_axis_read_desc(m_axis_desc_read),
-        .m_axis_read_desc_status(s_axis_status_read),
-        .m_axis_read_data(m_axis_read_data),
-        .s_axis_write_desc(m_axis_desc_write),
-        .m_axis_write_desc_status(s_axis_status_write),
-        .s_axis_write_data(m_axis_accum),
-        .m_axi(m_axi)
-    );
-
-endmodule : reflectometer_and_dma_wrapper

designs/full_new_reflectometer/tests/full_reflectometer_test/reflectometer_ip.sv

@@ -1,245 +0,0 @@
-`timescale 1 ns / 1 ns
-
-module reflectometer_top #(
-    // parameters for base reflectometer works
-    parameter int unsigned DAC_DATA_WIDTH = 14,
-    parameter int unsigned ADC_DATA_WIDTH = 12,
-    parameter int unsigned PACK_FACTOR = 1,
-    parameter int unsigned PROCESS_MODE = 0,
-    parameter int unsigned ZERO_LEVEL = 8192,
-    parameter int unsigned ACCUM_WIDTH = 32,
-    parameter int unsigned N_MAX = 4096,
-    parameter int unsigned PACKET_SIZE = 1024,
-    parameter int unsigned RD_FIFO_WIDTH = 32,
-
-        // parameters for DMA and interfaces
-    parameter int unsigned ADDR_W             = 16,
-    parameter int unsigned DATA_W             = 32,
-    parameter int unsigned USER_W             = 1
-)
-(
-    input  logic                       ctrl_clk,
-    input  logic                       rst_n,
-    output  wire                       locked,
-
-    axi4l_if.slave                     s_axil,
-    axis_if.master                     m_axis_accum,
-    axis_if.slave                      s_axis_status_read,
-    axis_if.slave                      s_axis_status_write,
-    axis_if.master                     m_axis_desc_read,
-    axis_if.master                     m_axis_desc_write,
-
-        // DAC
-    output  wire                        dac_clk_o,
-    output  wire [DAC_DATA_WIDTH-1:0]   dac_data,
-    output  wire                        dac_wrt,
-
-    // ADC
-    output  wire                        adc_clk_o,
-    input   wire [ADC_DATA_WIDTH-1:0]   adc_data,
-    input   wire                        adc_otr
-
-
-);
-
-wire workflow_done, processing_done;
-
-    // -------------------------------------------------------------------------
-    // Generated clocks for controller
-    // Need to create this IP in Vivado:
-    //  input  resetn
-    //  input  clk_200          : 200 MHz                  : Reference clock
-    //  output clk_adc_65       : 65 MHz                   : ADC RTL clock
-    //  output clk_adc_65_180   : 65 MHz, phase 180 deg.   : ADC PHY clock
-    //  output clk_adc_125      : 125 MHz                  : DAC RTL clock
-    //  output clk_adc_125_180  : 125 MHz, phase 180 deg.  : DAC PHY clock
-    //  output locked
-    // -------------------------------------------------------------------------
-    wire clk_sampler, clk_generator, clk_locked;
-
-    clk_wiz_0 clk_wiz_inst
-    (
-        // Clock in ports
-        .clk_200(ctrl_clk),
-        // Clock out ports  
-        .clk_adc_65(clk_sampler),
-        .clk_adc_65_180(adc_clk_o),
-        .clk_dac_125(clk_generator),
-        .clk_dac_125_180(dac_clk_o),
-        // Status and control signals               
-        .reset(~rst_n), 
-        .locked(clk_locked)
-    );
-
-    assign locked = clk_locked;
-
-    // -------------------------------------------------------------------------
-    // Controller reset
-    // Use both external reset and clk_wiz lock
-    // -------------------------------------------------------------------------
-    wire ctrl_rst_n = rst_n & clk_locked;
-
-    // -------------------------------------------------------------------------
-    // Controller
-    // -------------------------------------------------------------------------
-    wire [31:0]               dac_pulse_width;
-    wire [31:0]               dac_pulse_period;
-    wire [DAC_DATA_WIDTH-1:0] dac_pulse_height;
-    wire [15:0]               dac_pulse_num;
-
-    wire [31:0]               adc_pulse_period;
-    wire [15:0]               adc_pulse_num;
-    wire [31:0]               adc_window_size;
-
-    wire                      dac_start;
-    wire                      adc_start;
-    wire                      dac_rst;
-    wire                      adc_rst;
-
-    controller_wrapper_axil #(
-        .ADDR_W(ADDR_W),
-        .DATA_W(DATA_W),
-        .USER_W(USER_W),
-        .DAC_DATA_WIDTH(DAC_DATA_WIDTH)
-    ) controller_wrapper_axil_inst
-    (
-        .ctrl_clk(ctrl_clk),
-        .dac_clk_in(clk_generator),
-        .adc_clk_in(clk_sampler),
-        .rst_n(ctrl_rst_n),
-
-        .s_axil(s_axil),
-
-        .workflow_done(workflow_done),
-        .processing_done(processing_done),
-
-        .adc_window_size(adc_window_size),
-        .dac_pulse_width(dac_pulse_width),
-        .dac_pulse_period(dac_pulse_period),
-        .dac_pulse_height(dac_pulse_height),
-        .dac_pulse_num(dac_pulse_num),
-        .adc_pulse_period(adc_pulse_period),
-        .adc_pulse_num(adc_pulse_num),
-        .dac_start(dac_start),
-        .adc_start(adc_start),
-        .dac_rst(dac_rst),
-        .adc_rst(adc_rst),
-
-        .s_axis_status_read(s_axis_status_read),
-        .s_axis_status_write(s_axis_status_write),
-        .m_axis_desc_read(m_axis_desc_read),
-        .m_axis_desc_write(m_axis_desc_write)
-    );
-
-    //------------------------------------------------------------
-    // DAC -> ADC CDC
-    //------------------------------------------------------------
-    (* ASYNC_REG = "TRUE" *)    logic [2:0] stretch;    // 125/65~=2. Чтобы поймать единичный импульс, растянем его во времени
-    (* ASYNC_REG = "TRUE" *)    logic [1:0] sync_DA;
-                                wire        dac_done_stretched;
-
-    wire generator_done, generator_request;
-    wire sampler_done, sampler_request;
-    
-    always_ff @(posedge clk_generator or posedge dac_rst)
-    begin
-        if (dac_rst)
-            stretch <= 0;
-        else begin
-            stretch[0] <= generator_done;
-            stretch[1] <= stretch[0];
-            stretch[2] <= stretch[1];
-        end
-    end
-    assign dac_done_stretched = |stretch;
-
-    always_ff @(posedge clk_sampler or posedge adc_rst) begin
-        if (adc_rst)
-            sync_DA <= 0;
-        else begin
-            sync_DA[0] <= dac_done_stretched;
-            sync_DA[1] <= sync_DA[0];
-        end
-    end
-    assign sampler_request = sync_DA[1];
-
-    //------------------------------------------------------------
-    // ADC -> DAC CDC
-    //------------------------------------------------------------
-    (* ASYNC_REG = "TRUE" *)    logic [1:0] sync_AD;
-
-    always_ff @(posedge clk_generator or posedge dac_rst) begin
-        if (dac_rst)
-            sync_AD <= 0;
-        else begin
-            sync_AD[0] <= sampler_done;
-            sync_AD[1] <= sync_AD[0];
-        end
-    end
-    assign generator_request = sync_AD[1];
-
-    //------------------------------------------------------------
-    // Generator (DAC)
-    //------------------------------------------------------------
-    generator #(
-        .DATA_WIDTH(DAC_DATA_WIDTH),
-        .ZERO_LEVEL(ZERO_LEVEL)
-    ) generator_inst (
-        .clk_dac(clk_generator),
-        .rst(dac_rst),
-        .start(dac_start),
-        .pulse_width(dac_pulse_width),
-        .pulse_period(dac_pulse_period),
-        .pulse_height(dac_pulse_height),
-        .pulse_num(dac_pulse_num),
-        .dac_out(dac_data),
-        .done(generator_done),
-        .request(generator_request)
-    );
-    assign dac_wrt = dac_clk_o;
-
-    // -------------------------------------------------------------------------
-    // Sampler (ADC)
-    // -------------------------------------------------------------------------
-    wire [ADC_DATA_WIDTH*PACK_FACTOR-1:0]   sampler_m_axis_tdata;
-    wire                                    sampler_m_axis_tvalid;
-
-    sampler #(
-        .DATA_WIDTH(ADC_DATA_WIDTH),
-        .PACK_FACTOR(PACK_FACTOR),
-        .PROCESS_MODE(PROCESS_MODE)
-    ) sampler_inst (
-        .clk_in(clk_sampler),
-        .rst(adc_rst),
-        .data_in(adc_data),
-        .out_of_range(adc_otr),
-        .m_axis_tdata(sampler_m_axis_tdata),
-        .m_axis_tvalid(sampler_m_axis_tvalid),
-        .smp_num(adc_pulse_period),
-        .done(sampler_done),
-        .request(sampler_request)
-    );
-
-    accumulator_top #(
-        .DATA_WIDTH(ADC_DATA_WIDTH),
-        .ACCUM_WIDTH(ACCUM_WIDTH),
-        .N_MAX(N_MAX),
-        .PACKET_SIZE(PACKET_SIZE),
-        .RW_WIDTH(RD_FIFO_WIDTH)
-    ) accumulator_top_inst (
-        .clk_in(clk_sampler),
-        .rst(adc_rst),
-        .s_axis_tdata(sampler_m_axis_tdata),
-        .s_axis_tvalid(sampler_m_axis_tvalid),
-        .start(adc_start),
-        .smp_num(adc_pulse_period),
-        .seq_num(adc_pulse_num),
-        .window_size(adc_window_size),
-        .dma_clk_in(ctrl_clk),
-        .req_ready(1'b1),
-        .m_axis_accum(m_axis_accum),
-        .finish(workflow_done),
-        .accum_done(processing_done)
-    );
-
-endmodule