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clk_wiz_libs files fo questa

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otroubi
2026-09-03 16:02:20 +03:00
parent 86c555d298
commit 703e32ad5e
20 changed files with 10507 additions and 425 deletions
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designs/full_new_reflectometer/tests/full_reflectometer_test/Makefile
+2 -3
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@@ -35,7 +35,6 @@ VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller_pkg.sv
VERILOG_SOURCES += $(RTL_DIR)/axis_defaults_helper.sv
VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller.sv
VERILOG_SOURCES += $(RTL_DIR)/axi_dma_wrapper_if.sv
VERILOG_SOURCES += $(RTL_DIR)/wrapper_controller_dma.sv
VERILOG_SOURCES += $(RTL_ACCUM_DIR)/adder.sv
VERILOG_SOURCES += $(RTL_ACCUM_DIR)/out_axis_fifo.sv
VERILOG_SOURCES += $(RTL_ACCUM_DIR)/accum.sv
@@ -47,8 +46,8 @@ VERILOG_SOURCES += $(RTL_CLK_DIR)/clk_wiz_0.v
VERILOG_SOURCES += $(PWD)/adc_model.sv
VERILOG_SOURCES += $(PWD)/dac_model.sv
VERILOG_SOURCES += $(PWD)/reflectometer_ip.sv
VERILOG_SOURCES += $(PWD)/reflectometer_and_dma_wrapper.sv
VERILOG_SOURCES += $(RTL_DIR)/reflectometer_ip.sv
VERILOG_SOURCES += $(RTL_DIR)/reflectometer_and_dma_wrapper.sv
VERILOG_SOURCES += $(PWD)/tb_full_reflectometer.sv
VERILOG_SOURCES += /mnt/c/Xilinx/Vivado/2021.2/data/verilog/src/glbl.v
designs/full_new_reflectometer/tests/full_reflectometer_test/reflectometer_and_dma_wrapper.sv
-177
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@@ -1,177 +0,0 @@
`timescale 1 ns / 1 ns
module reflectometer_and_dma_wrapper
#(
// parameters for base reflectometer works
parameter int unsigned DAC_DATA_WIDTH = 14,
parameter int unsigned ADC_DATA_WIDTH = 12,
parameter int unsigned PACK_FACTOR = 1,
parameter int unsigned PROCESS_MODE = 0,
parameter int unsigned ZERO_LEVEL = 8192,
parameter int unsigned ACCUM_WIDTH = 32,
parameter int unsigned N_MAX = 4096,
parameter int unsigned PACKET_SIZE = 1024,
parameter int unsigned RD_FIFO_WIDTH = 32,
// parameters for DMA and interfaces
parameter int unsigned ADDR_W = 16,
parameter int unsigned DATA_W = 32,
parameter int unsigned USER_W = 1,
parameter int unsigned AXI_DATA_WIDTH = 32,
parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
parameter int unsigned AXI_USER_WIDTH = 1,
parameter int unsigned AXI_MAX_BURST_LEN = 16,
parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
parameter int unsigned AXIS_LAST_ENABLE = 1,
parameter int unsigned AXIS_ID_ENABLE = 1,
parameter int unsigned AXIS_DEST_ENABLE = 0,
parameter int unsigned AXIS_USER_ENABLE = 1,
parameter int unsigned ENABLE_SG = 0,
parameter int unsigned ENABLE_UNALIGNED = 0,
parameter int unsigned PIPELINE_OUTPUT = 0
)
(
input logic ctrl_clk,
input logic rst_n,
output wire locked,
axi4l_if.slave s_axil,
axi4_if.master m_axi,
// todo
axis_if.master m_axis_read_data,
// DAC
output wire dac_clk_o,
output wire [DAC_DATA_WIDTH-1:0] dac_data,
output wire dac_wrt,
// ADC
output wire adc_clk_o,
input wire [ADC_DATA_WIDTH-1:0] adc_data,
input wire adc_otr
);
axis_if #(
.DATA_W($bits(dma_read_status_t)),
.KEEP_W(($bits(dma_read_status_t)+7)/8),
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
) s_axis_status_read (
.aclk(ctrl_clk),
.aresetn(rst_n)
);
axis_if #(
.DATA_W($bits(dma_write_status_t)),
.KEEP_W(($bits(dma_write_status_t)+7)/8),
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
) s_axis_status_write (
.aclk(ctrl_clk),
.aresetn(rst_n)
);
axis_if #(
.DATA_W($bits(dma_read_desc_t)),
.KEEP_W(($bits(dma_read_desc_t)+7)/8),
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
) m_axis_desc_read (
.aclk(ctrl_clk),
.aresetn(rst_n)
);
axis_if #(
.DATA_W($bits(dma_write_desc_t)),
.KEEP_W(($bits(dma_write_desc_t)+7)/8),
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
) m_axis_desc_write (
.aclk(ctrl_clk),
.aresetn(rst_n)
);
axis_if #(
.DATA_W(RD_FIFO_WIDTH),
.KEEP_W((RD_FIFO_WIDTH+7)/8),
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
) m_axis_accum (
.aclk(ctrl_clk),
.aresetn(rst_n)
);
reflectometer_top #(
.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
.PACK_FACTOR(PACK_FACTOR),
.PROCESS_MODE(PROCESS_MODE),
.ZERO_LEVEL(ZERO_LEVEL),
.ACCUM_WIDTH(ACCUM_WIDTH),
.N_MAX(N_MAX),
.PACKET_SIZE(PACKET_SIZE),
.RD_FIFO_WIDTH(RD_FIFO_WIDTH)
) reflectometer_top_inst (
.ctrl_clk(ctrl_clk),
.rst_n(rst_n),
.locked(locked),
.s_axil(s_axil),
.m_axis_accum(m_axis_accum),
.s_axis_status_read(s_axis_status_read),
.s_axis_status_write(s_axis_status_write),
.m_axis_desc_read(m_axis_desc_read),
.m_axis_desc_write(m_axis_desc_write),
.dac_clk_o(dac_clk_o),
.dac_data(dac_data),
.dac_wrt(dac_wrt),
.adc_clk_o(adc_clk_o),
.adc_data(adc_data),
.adc_otr(adc_otr)
);
//------------------------------------------------------------
// DMA
//------------------------------------------------------------
axi_dma_wrapper #(
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_USER_WIDTH(AXI_USER_WIDTH),
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
.AXIS_ID_ENABLE(AXIS_ID_ENABLE),
.AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
.AXIS_USER_ENABLE(AXIS_USER_ENABLE),
.ENABLE_SG(ENABLE_SG),
.ENABLE_UNALIGNED(ENABLE_UNALIGNED)
) axi_dma_wrapper_inst
(
.clk(ctrl_clk),
.rst(!rst_n),
.s_axis_read_desc(m_axis_desc_read),
.m_axis_read_desc_status(s_axis_status_read),
.m_axis_read_data(m_axis_read_data),
.s_axis_write_desc(m_axis_desc_write),
.m_axis_write_desc_status(s_axis_status_write),
.s_axis_write_data(m_axis_accum),
.m_axi(m_axi)
);
endmodule : reflectometer_and_dma_wrapper
designs/full_new_reflectometer/tests/full_reflectometer_test/reflectometer_ip.sv
-245
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@@ -1,245 +0,0 @@
`timescale 1 ns / 1 ns
module reflectometer_top #(
// parameters for base reflectometer works
parameter int unsigned DAC_DATA_WIDTH = 14,
parameter int unsigned ADC_DATA_WIDTH = 12,
parameter int unsigned PACK_FACTOR = 1,
parameter int unsigned PROCESS_MODE = 0,
parameter int unsigned ZERO_LEVEL = 8192,
parameter int unsigned ACCUM_WIDTH = 32,
parameter int unsigned N_MAX = 4096,
parameter int unsigned PACKET_SIZE = 1024,
parameter int unsigned RD_FIFO_WIDTH = 32,
// parameters for DMA and interfaces
parameter int unsigned ADDR_W = 16,
parameter int unsigned DATA_W = 32,
parameter int unsigned USER_W = 1
)
(
input logic ctrl_clk,
input logic rst_n,
output wire locked,
axi4l_if.slave s_axil,
axis_if.master m_axis_accum,
axis_if.slave s_axis_status_read,
axis_if.slave s_axis_status_write,
axis_if.master m_axis_desc_read,
axis_if.master m_axis_desc_write,
// DAC
output wire dac_clk_o,
output wire [DAC_DATA_WIDTH-1:0] dac_data,
output wire dac_wrt,
// ADC
output wire adc_clk_o,
input wire [ADC_DATA_WIDTH-1:0] adc_data,
input wire adc_otr
);
wire workflow_done, processing_done;
// -------------------------------------------------------------------------
// Generated clocks for controller
// Need to create this IP in Vivado:
// input resetn
// input clk_200 : 200 MHz : Reference clock
// output clk_adc_65 : 65 MHz : ADC RTL clock
// output clk_adc_65_180 : 65 MHz, phase 180 deg. : ADC PHY clock
// output clk_adc_125 : 125 MHz : DAC RTL clock
// output clk_adc_125_180 : 125 MHz, phase 180 deg. : DAC PHY clock
// output locked
// -------------------------------------------------------------------------
wire clk_sampler, clk_generator, clk_locked;
clk_wiz_0 clk_wiz_inst
(
// Clock in ports
.clk_200(ctrl_clk),
// Clock out ports
.clk_adc_65(clk_sampler),
.clk_adc_65_180(adc_clk_o),
.clk_dac_125(clk_generator),
.clk_dac_125_180(dac_clk_o),
// Status and control signals
.reset(~rst_n),
.locked(clk_locked)
);
assign locked = clk_locked;
// -------------------------------------------------------------------------
// Controller reset
// Use both external reset and clk_wiz lock
// -------------------------------------------------------------------------
wire ctrl_rst_n = rst_n & clk_locked;
// -------------------------------------------------------------------------
// Controller
// -------------------------------------------------------------------------
wire [31:0] dac_pulse_width;
wire [31:0] dac_pulse_period;
wire [DAC_DATA_WIDTH-1:0] dac_pulse_height;
wire [15:0] dac_pulse_num;
wire [31:0] adc_pulse_period;
wire [15:0] adc_pulse_num;
wire [31:0] adc_window_size;
wire dac_start;
wire adc_start;
wire dac_rst;
wire adc_rst;
controller_wrapper_axil #(
.ADDR_W(ADDR_W),
.DATA_W(DATA_W),
.USER_W(USER_W),
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
) controller_wrapper_axil_inst
(
.ctrl_clk(ctrl_clk),
.dac_clk_in(clk_generator),
.adc_clk_in(clk_sampler),
.rst_n(ctrl_rst_n),
.s_axil(s_axil),
.workflow_done(workflow_done),
.processing_done(processing_done),
.adc_window_size(adc_window_size),
.dac_pulse_width(dac_pulse_width),
.dac_pulse_period(dac_pulse_period),
.dac_pulse_height(dac_pulse_height),
.dac_pulse_num(dac_pulse_num),
.adc_pulse_period(adc_pulse_period),
.adc_pulse_num(adc_pulse_num),
.dac_start(dac_start),
.adc_start(adc_start),
.dac_rst(dac_rst),
.adc_rst(adc_rst),
.s_axis_status_read(s_axis_status_read),
.s_axis_status_write(s_axis_status_write),
.m_axis_desc_read(m_axis_desc_read),
.m_axis_desc_write(m_axis_desc_write)
);
//------------------------------------------------------------
// DAC -> ADC CDC
//------------------------------------------------------------
(* ASYNC_REG = "TRUE" *) logic [2:0] stretch; // 125/65~=2. Чтобы поймать единичный импульс, растянем его во времени
(* ASYNC_REG = "TRUE" *) logic [1:0] sync_DA;
wire dac_done_stretched;
wire generator_done, generator_request;
wire sampler_done, sampler_request;
always_ff @(posedge clk_generator or posedge dac_rst)
begin
if (dac_rst)
stretch <= 0;
else begin
stretch[0] <= generator_done;
stretch[1] <= stretch[0];
stretch[2] <= stretch[1];
end
end
assign dac_done_stretched = |stretch;
always_ff @(posedge clk_sampler or posedge adc_rst) begin
if (adc_rst)
sync_DA <= 0;
else begin
sync_DA[0] <= dac_done_stretched;
sync_DA[1] <= sync_DA[0];
end
end
assign sampler_request = sync_DA[1];
//------------------------------------------------------------
// ADC -> DAC CDC
//------------------------------------------------------------
(* ASYNC_REG = "TRUE" *) logic [1:0] sync_AD;
always_ff @(posedge clk_generator or posedge dac_rst) begin
if (dac_rst)
sync_AD <= 0;
else begin
sync_AD[0] <= sampler_done;
sync_AD[1] <= sync_AD[0];
end
end
assign generator_request = sync_AD[1];
//------------------------------------------------------------
// Generator (DAC)
//------------------------------------------------------------
generator #(
.DATA_WIDTH(DAC_DATA_WIDTH),
.ZERO_LEVEL(ZERO_LEVEL)
) generator_inst (
.clk_dac(clk_generator),
.rst(dac_rst),
.start(dac_start),
.pulse_width(dac_pulse_width),
.pulse_period(dac_pulse_period),
.pulse_height(dac_pulse_height),
.pulse_num(dac_pulse_num),
.dac_out(dac_data),
.done(generator_done),
.request(generator_request)
);
assign dac_wrt = dac_clk_o;
// -------------------------------------------------------------------------
// Sampler (ADC)
// -------------------------------------------------------------------------
wire [ADC_DATA_WIDTH*PACK_FACTOR-1:0] sampler_m_axis_tdata;
wire sampler_m_axis_tvalid;
sampler #(
.DATA_WIDTH(ADC_DATA_WIDTH),
.PACK_FACTOR(PACK_FACTOR),
.PROCESS_MODE(PROCESS_MODE)
) sampler_inst (
.clk_in(clk_sampler),
.rst(adc_rst),
.data_in(adc_data),
.out_of_range(adc_otr),
.m_axis_tdata(sampler_m_axis_tdata),
.m_axis_tvalid(sampler_m_axis_tvalid),
.smp_num(adc_pulse_period),
.done(sampler_done),
.request(sampler_request)
);
accumulator_top #(
.DATA_WIDTH(ADC_DATA_WIDTH),
.ACCUM_WIDTH(ACCUM_WIDTH),
.N_MAX(N_MAX),
.PACKET_SIZE(PACKET_SIZE),
.RW_WIDTH(RD_FIFO_WIDTH)
) accumulator_top_inst (
.clk_in(clk_sampler),
.rst(adc_rst),
.s_axis_tdata(sampler_m_axis_tdata),
.s_axis_tvalid(sampler_m_axis_tvalid),
.start(adc_start),
.smp_num(adc_pulse_period),
.seq_num(adc_pulse_num),
.window_size(adc_window_size),
.dma_clk_in(ctrl_clk),
.req_ready(1'b1),
.m_axis_accum(m_axis_accum),
.finish(workflow_done),
.accum_done(processing_done)
);
endmodule