From 64f94a90e677aea26f3125d467060b1a13b19298 Mon Sep 17 00:00:00 2001
From: "babintsev.lv" <babintsev.lv@mipt.ru>
Date: Wed, 8 Jul 2026 17:47:56 +0300
Subject: [PATCH] add: virtual DAC (100%) and ADC (80%) upd: makefile

---
 designs/reflectometer_base/Makefile           |  2 +
 designs/reflectometer_base/adc_model.sv       | 53 ++++++++++++++++
 designs/reflectometer_base/dac_model.sv       | 60 +++++++++++++++++++
 .../reflectometer_base/tb_reflectometer.sv    |  2 +-
 4 files changed, 116 insertions(+), 1 deletion(-)
 create mode 100644 designs/reflectometer_base/adc_model.sv
 create mode 100644 designs/reflectometer_base/dac_model.sv

diff --git a/designs/reflectometer_base/Makefile b/designs/reflectometer_base/Makefile
index caa7662..c8c57f7 100644
--- a/designs/reflectometer_base/Makefile
+++ b/designs/reflectometer_base/Makefile
@@ -17,6 +17,8 @@ RTL_DIR = ../../rtl
 include ../../scripts/vivado.mk
 
 SYN_FILES += reflectometer.sv
+SYN_FILES += dac_model.sv
+SYN_FILES += adc_model.sv
 SYN_FILES += tb_reflectometer.sv
 SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
 
diff --git a/designs/reflectometer_base/adc_model.sv b/designs/reflectometer_base/adc_model.sv
new file mode 100644
index 0000000..c0e7df6
--- /dev/null
+++ b/designs/reflectometer_base/adc_model.sv
@@ -0,0 +1,53 @@
+// AN9238 virtual ADC model (1 port)
+
+module virtual_adc_model #(
+    parameter int unsigned ADC_DATA_WIDTH = 12,
+
+    // Bipolar input range: +/- VOLTAGE_RANGE
+    parameter real VOLTAGE_RANGE = 1.0,
+
+    // Analog input correction
+    parameter real VOLTAGE_GAIN  = 0.2,
+    parameter real GROUND_BIAS   = 0.0,
+
+    // ADC timing parameters
+    parameter time CONVERSION_DELAY = 150ps
+)(
+    input  logic                         clk_i,
+    input  real                          voltage_i,
+
+    output logic                         otr_o,
+    output logic [ADC_DATA_WIDTH-1:0]    data_o
+);
+
+    localparam int unsigned ZERO_CODE = (1 << (ADC_DATA_WIDTH - 1));
+    localparam real VOLTAGE_STEP = VOLTAGE_RANGE / real'(ZERO_CODE);
+
+    //------------------------------------------------------------
+    // Convert analog voltage to ADC code TODO: add OTR check
+    //------------------------------------------------------------
+    function automatic real code_to_voltage(
+        input logic [ADC_DATA_WIDTH-1:0] code
+    );
+        return (int'(code) - int'(ZERO_CODE)) * VOLTAGE_STEP;
+    endfunction
+
+    //------------------------------------------------------------
+    // Initial state
+    //------------------------------------------------------------
+    initial begin
+        data_o = ZERO_CODE; // 0V
+        otr_o  = 0;
+    end
+
+    //------------------------------------------------------------
+    // Update analog output
+    //------------------------------------------------------------
+    always @(posedge clk_i) begin
+        #(CONVERSION_DELAY);
+        data_o = ;
+        otr_o = ;
+        
+    end
+
+endmodule
diff --git a/designs/reflectometer_base/dac_model.sv b/designs/reflectometer_base/dac_model.sv
new file mode 100644
index 0000000..4ba474b
--- /dev/null
+++ b/designs/reflectometer_base/dac_model.sv
@@ -0,0 +1,60 @@
+// AN9767 model (1 port)
+
+module virtual_dac_model #(
+    parameter int unsigned DAC_DATA_WIDTH = 14,
+
+    // Bipolar output range: +/- VOLTAGE_RANGE
+    parameter real VOLTAGE_RANGE = 5.0,
+
+    // Analog output correction
+    parameter real VOLTAGE_GAIN  = 1.0,
+    parameter real GROUND_BIAS   = 0.0,
+
+    // DAC timing parameters
+    parameter time TRANSMISSION_DELAY = 150ps,
+    parameter time CONVERSION_DELAY   = 150ps
+)(
+    input  logic                      clk_i,
+    input  logic                      wrt_i,
+    input  logic [DAC_DATA_WIDTH-1:0] data_i,
+
+    output real                       voltage_o
+);
+
+    localparam int unsigned ZERO_CODE = (1 << (DAC_DATA_WIDTH - 1));
+    localparam real VOLTAGE_STEP = VOLTAGE_RANGE / real'(ZERO_CODE);
+
+    logic [DAC_DATA_WIDTH-1:0] dac_code;
+
+    //------------------------------------------------------------
+    // Convert DAC code to analog voltage
+    //------------------------------------------------------------
+    function automatic real code_to_voltage( input logic [DAC_DATA_WIDTH-1:0] code);
+        return (int'(code) - int'(ZERO_CODE)) * VOLTAGE_STEP;
+    endfunction
+
+    //------------------------------------------------------------
+    // Initial state
+    //------------------------------------------------------------
+    initial begin
+        dac_code  = '0;
+        voltage_o = code_to_voltage('0) * VOLTAGE_GAIN + GROUND_BIAS;
+    end
+
+    //------------------------------------------------------------
+    // Latch new DAC code
+    //------------------------------------------------------------
+    always @(posedge wrt_i) begin
+        #(TRANSMISSION_DELAY);
+        dac_code = data_i;
+    end
+
+    //------------------------------------------------------------
+    // Update analog output
+    //------------------------------------------------------------
+    always @(posedge clk_i) begin
+        #(CONVERSION_DELAY);
+        voltage_o = code_to_voltage(dac_code) * VOLTAGE_GAIN + GROUND_BIAS;
+    end
+
+endmodule
diff --git a/designs/reflectometer_base/tb_reflectometer.sv b/designs/reflectometer_base/tb_reflectometer.sv
index 7e75b34..fbb60c7 100644
--- a/designs/reflectometer_base/tb_reflectometer.sv
+++ b/designs/reflectometer_base/tb_reflectometer.sv
@@ -66,7 +66,7 @@ module tb_reflectometer;
     //------------------------------------------------------------
     // Virtual DAC
     //------------------------------------------------------------
-
+    
     //------------------------------------------------------------
     // Virtual ADC
     //------------------------------------------------------------