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rtl: sampler validation changes

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otroubi
2026-06-10 17:07:40 +03:00
parent c0714f271e
commit 64843b462d
2 changed files with 59 additions and 210 deletions
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33
rtl/sampler/src/sampler.sv
View File

@ -12,16 +12,16 @@ module sampler
input [DATA_WIDTH-1:0] data_in,
input out_of_range,
input [31:0] smp_num,
input request,
input done,
output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
output logic m_axis_tvalid,
output logic done
output logic request
);
logic [DATA_WIDTH-1:0] data_converted;
logic out_of_range_reg;
logic [31:0] smp_num_reg, cnt_smp_num;
logic enable;
(* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted;
(* MARK_DEBUG="true" *) logic out_of_range_reg;
(* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num;
(* MARK_DEBUG="true" *) logic enable, enable_d;
generate
if (PROCESS_MODE) begin
@ -53,8 +53,8 @@ module sampler
end
endgenerate
logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
logic buffer_ready;
(* MARK_DEBUG="true" *) logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
(* MARK_DEBUG="true" *) logic buffer_ready;
logic [$clog2(PACK_FACTOR):0] cnt;
@ -67,31 +67,32 @@ module sampler
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= 0;
done <= 0;
request <= 0;
end
else begin
buffer_ready <= 0;
if (!enable) begin
if (request && done) begin
enable <= 1;
done <= 0;
request <= 0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end else begin
done <= 1;
request <= 1;
end
end else begin
if (cnt_smp_num != smp_num_reg) begin
cnt_smp_num <= cnt_smp_num +1;
buffer_ready <= 1;
if (!out_of_range_reg) begin
buffer <= data_converted;
buffer_ready <= 1;
end
end
else begin
cnt_smp_num <= '0;
buffer_ready <= 0;
enable <= 0;
buffer <= '0;
end
end
end
@ -105,27 +106,27 @@ module sampler
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= 0;
done <= 0;
request <= 0;
end
else begin
buffer_ready <= 0;
if (!enable) begin
if (request && done) begin
enable <= 1;
done <= 0;
request <= 0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end else begin
done <= 1;
request <= 1;
end
end else begin
if (cnt_smp_num != smp_num_reg) begin
cnt_smp_num <= cnt_smp_num +1;
buffer_ready <= 1;
if (!out_of_range_reg) begin
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
if (cnt == PACK_FACTOR-1) begin
cnt <= 0;
buffer_ready <= 1;
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
end
else begin

220
rtl/sampler/tests/sampler_tb.sv
View File

@ -7,10 +7,6 @@ module sampler_tb;
localparam PROCESS_MODE = 0;
localparam CLK_PERIOD = 15.3846;
// =====================================================
// DUT SIGNALS
// =====================================================
logic clk;
logic rst;
@ -25,16 +21,7 @@ module sampler_tb;
logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
logic m_axis_tvalid;
// =====================================================
// SCOREBOARD
// =====================================================
int received_count;
int expected_count;
// =====================================================
// DUT
// =====================================================
sampler #(
.DATA_WIDTH (DATA_WIDTH),
@ -48,18 +35,17 @@ module sampler_tb;
.out_of_range (out_of_range),
.smp_num (smp_num),
.done (request),
.done (done),
.m_axis_tdata (m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.request (done)
.request (request)
);
// =====================================================
// CLOCK
// =====================================================
initial begin
clk = 0;
forever #(CLK_PERIOD/2) clk = ~clk;
@ -68,112 +54,36 @@ module sampler_tb;
// =====================================================
// RESET
// =====================================================
initial begin
rst = 1;
data_in = 0;
out_of_range = 0;
done = 0;
smp_num = 0;
repeat(5) @(posedge clk);
rst = 0;
end
// =====================================================
// RECEIVED COUNTER
// OUTPUT COUNTER
// =====================================================
always @(posedge clk) begin
if (m_axis_tvalid)
received_count++;
end
// =====================================================
// CONFIG
// FEED DATA
// =====================================================
task automatic set_config(input int n);
begin
smp_num = n;
@(posedge clk);
end
endtask
// =====================================================
// WAIT SAMPLER START
// =====================================================
task automatic wait_sampler_start;
begin
wait(dut.enable == 1'b1);
// @(negedge clk);
end
endtask
// =====================================================
// HANDSHAKE
// =====================================================
task automatic synchronize_sampler(
input bit sampler_first,
input int delay_before_ack,
input int ack_duration
);
begin
if (sampler_first) begin
repeat(delay_before_ack)
@(posedge clk);
done <= 1'b1;
wait(request == 1'b1);
repeat(ack_duration)
@(posedge clk);
done <= 1'b0;
end
else begin
wait(request == 1'b1);
repeat(delay_before_ack)
@(posedge clk);
done <= 1'b1;
repeat(ack_duration)
@(posedge clk);
done <= 1'b0;
end
end
endtask
// =====================================================
// DATA FEED
// =====================================================
task automatic feed_data_stream(
input int num_words,
input bit random_data,
input bit random_out_of_range
);
logic [DATA_WIDTH-1:0] value;
bit oor;
begin
value = 1;
for (int i = 0; i < num_words; i++) begin
@ -188,157 +98,95 @@ module sampler_tb;
else
oor = 0;
data_in = value;
out_of_range = oor;
if (!oor)
expected_count++;
@(posedge clk);
end
out_of_range <= 0;
out_of_range = 0;
end
endtask
// =====================================================
// SINGLE TEST
// TEST CASE
// =====================================================
task automatic run_test_case(
input int n,
input int delay_before_ack,
input int ack_duration,
input bit sampler_first,
input bit random_data,
input bit random_out_of_range
);
begin
received_count = 0;
expected_count = 0;
data_in = 0;
out_of_range = 0;
done = 0;
set_config(n);
smp_num = n;
synchronize_sampler(
sampler_first,
delay_before_ack,
1
);
feed_data_stream(
n,
random_data,
random_out_of_range
);
repeat(30)
// handshake
@(posedge clk);
done <= 1'b1;
wait(request == 1'b1);
@(posedge clk);
done <= 1'b0;
$display(
"Expected=%0d Received=%0d",
expected_count,
received_count
);
// wait enable
wait(dut.enable == 1'b1);
if (received_count == expected_count)
// feed data
feed_data_stream(n + 10, random_data, random_out_of_range);
// wait completion
wait(dut.enable == 1'b0);
$display("Expected smp_num=%0d Received=%0d", smp_num, received_count);
if (received_count == smp_num)
$display("[OK]");
else
$display("[ERROR]");
repeat(10)
@(posedge clk);
repeat(10) @(posedge clk);
end
endtask
// =====================================================
// RANDOM STRESS
// RANDOM TESTS
// =====================================================
task automatic random_stress_test;
int n;
int d;
int a;
bit sf;
begin
for (int i = 0; i < 20; i++) begin
n = $urandom_range(5,20);
d = $urandom_range(0,5);
a = $urandom_range(1,5);
sf = $urandom_range(0,1);
$display("");
$display(
"--- TEST %0d --- n=%0d delay=%0d ack=%0d sf=%0b",
i, n, d, a, sf
);
$display("\n--- TEST %0d --- n=%0d", i, n);
run_test_case(
n,
d,
a,
sf,
1, // random data
1 // random out_of_range
1,
1
);
end
end
endtask
// =====================================================
// MAIN
// =====================================================
initial begin
wait(!rst);
$display("\n=== BASIC TEST ===");
run_test_case(10, 0, 0);
$display("");
$display("=== BASIC TEST ===");
run_test_case(
10,
2,
2,
1,
0,
0
);
$display("");
$display("=== OUT_OF_RANGE TEST ===");
run_test_case(
20,
1,
2,
1,
1,
1
);
$display("");
$display("=== RANDOM STRESS TEST ===");
$display("\n=== OUT_OF_RANGE TEST ===");
run_test_case(20, 1, 1);
$display("\n=== RANDOM STRESS TEST ===");
random_stress_test();
$display("");
$display("=== TEST FINISHED ===");
$display("\n=== TEST FINISHED ===");
$finish;
end