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rtl: sampler validation changes

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otroubi
2026-06-10 17:07:40 +03:00
parent c0714f271e
commit 64843b462d
2 changed files with 59 additions and 210 deletions
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33
rtl/sampler/src/sampler.sv
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@ -12,16 +12,16 @@ module sampler
input [DATA_WIDTH-1:0] data_in,
input out_of_range,
input [31:0] smp_num,
input request,
input done,
output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
output logic m_axis_tvalid,
output logic done
output logic request
);
logic [DATA_WIDTH-1:0] data_converted;
logic out_of_range_reg;
logic [31:0] smp_num_reg, cnt_smp_num;
logic enable;
(* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted;
(* MARK_DEBUG="true" *) logic out_of_range_reg;
(* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num;
(* MARK_DEBUG="true" *) logic enable, enable_d;
generate
if (PROCESS_MODE) begin
@ -53,8 +53,8 @@ module sampler
end
endgenerate
logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
logic buffer_ready;
(* MARK_DEBUG="true" *) logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
(* MARK_DEBUG="true" *) logic buffer_ready;
logic [$clog2(PACK_FACTOR):0] cnt;
@ -67,31 +67,32 @@ module sampler
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= 0;
done <= 0;
request <= 0;
end
else begin
buffer_ready <= 0;
if (!enable) begin
if (request && done) begin
enable <= 1;
done <= 0;
request <= 0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end else begin
done <= 1;
request <= 1;
end
end else begin
if (cnt_smp_num != smp_num_reg) begin
cnt_smp_num <= cnt_smp_num +1;
buffer_ready <= 1;
if (!out_of_range_reg) begin
buffer <= data_converted;
buffer_ready <= 1;
end
end
else begin
cnt_smp_num <= '0;
buffer_ready <= 0;
enable <= 0;
buffer <= '0;
end
end
end
@ -105,27 +106,27 @@ module sampler
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= 0;
done <= 0;
request <= 0;
end
else begin
buffer_ready <= 0;
if (!enable) begin
if (request && done) begin
enable <= 1;
done <= 0;
request <= 0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end else begin
done <= 1;
request <= 1;
end
end else begin
if (cnt_smp_num != smp_num_reg) begin
cnt_smp_num <= cnt_smp_num +1;
buffer_ready <= 1;
if (!out_of_range_reg) begin
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
if (cnt == PACK_FACTOR-1) begin
cnt <= 0;
buffer_ready <= 1;
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
end
else begin