change: sampler remark 2

rtl/sampler/src/sampler.sv

@@ -21,7 +21,7 @@ module sampler
   logic [DATA_WIDTH-1:0] data_converted;
   logic out_of_range_reg;
   logic [31:0] smp_num_reg, cnt_smp_num;
-  logic enable, enable_d;
+  logic enable;
     
     generate
        if (PROCESS_MODE) begin