From 5c1866d571bfa31650916449a4e8c98c48864227 Mon Sep 17 00:00:00 2001 From: Phil Date: Tue, 12 May 2026 13:25:44 +0300 Subject: [PATCH] chore: re-organise designs for better hierarchy --- designs/reflectometer/reflectometer.sv | 425 ----------- .../Makefile | 4 +- designs/reflectometer_base/debug.xdc | 1 + .../ip/clk_wiz_ctrl_inst.xci | 0 .../reflectometer.sv | 63 +- designs/reflectometer_prototype/Makefile | 53 ++ .../README.md | 0 .../debug.xdc | 185 +++-- .../ip/clk_wiz_ctrl_inst.xci | 689 ++++++++++++++++++ designs/reflectometer_prototype/prototype.sv | 172 +++++ designs/reflectometer_without_eth/Makefile | 0 designs/reflectometer_without_eth/debug.xdc | 153 ---- 12 files changed, 1071 insertions(+), 674 deletions(-) delete mode 100644 designs/reflectometer/reflectometer.sv rename designs/{reflectometer => reflectometer_base}/Makefile (95%) create mode 100644 designs/reflectometer_base/debug.xdc rename designs/{reflectometer => reflectometer_base}/ip/clk_wiz_ctrl_inst.xci (100%) rename designs/{reflectometer_without_eth => reflectometer_base}/reflectometer.sv (92%) create mode 100644 designs/reflectometer_prototype/Makefile rename designs/{reflectometer => reflectometer_prototype}/README.md (100%) rename designs/{reflectometer => reflectometer_prototype}/debug.xdc (52%) create mode 100644 designs/reflectometer_prototype/ip/clk_wiz_ctrl_inst.xci create mode 100644 designs/reflectometer_prototype/prototype.sv delete mode 100644 designs/reflectometer_without_eth/Makefile delete mode 100644 designs/reflectometer_without_eth/debug.xdc diff --git a/designs/reflectometer/reflectometer.sv b/designs/reflectometer/reflectometer.sv deleted file mode 100644 index 0437845..0000000 --- a/designs/reflectometer/reflectometer.sv +++ /dev/null @@ -1,425 +0,0 @@ -`timescale 1 ns / 1 ns - -module reflectometer_top #( - parameter int unsigned DAC_DATA_WIDTH = 14, - parameter int unsigned ADC_DATA_WIDTH = 12, - parameter PACK_FACTOR = 1, - parameter PROCESS_MODE = 0, - parameter ACCUM_WIDTH = 32, - parameter N_MAX = 4096, - parameter WINDOW_SIZE = 65, - parameter PACKET_SIZE = 1024 -)( - input sys_clk_p, - input sys_clk_n, - input rst_n, - - output [3:0] led, - - output e_reset, - output e_mdc, - inout e_mdio, - - output [3:0] rgmii_txd, - output rgmii_txctl, - output rgmii_txc, - input [3:0] rgmii_rxd, - input rgmii_rxctl, - input rgmii_rxc, - - // DAC - - (* MARK_DEBUG="true" *) output debug_dac, - - // ADC - output ch2_clk, - (* MARK_DEBUG="true" *) input [ADC_DATA_WIDTH-1:0] ch2_data, - input ch2_otr - -); - // temp - - wire p2_wrt; - wire [13:0] p2_data; - assign debug_dac = p2_data[13]; - // ------------------------------------------------------------------------- - // Internal GMII-side signals - // ------------------------------------------------------------------------- - wire [7:0] gmii_txd; - wire gmii_tx_en; - wire gmii_tx_er; - wire gmii_tx_clk; - wire gmii_crs; - wire gmii_col; - wire [7:0] gmii_rxd_i; - wire gmii_rx_dv; - wire gmii_rx_er; - wire gmii_rx_clk; - - wire [31:0] pack_total_len; - - wire e_rx_dv; - wire [7:0] e_rxd; - wire e_tx_en; - wire [7:0] e_txd; - wire e_rst_n; - wire sys_clk; - - wire duplex_mode; - - - assign duplex_mode = 1'b1; - - // ------------------------------------------------------------------------- - // System clock buffer (200 MHz differential input) - // ------------------------------------------------------------------------- - IBUFDS sys_clk_ibufgds ( - .O (sys_clk), - .I (sys_clk_p), - .IB (sys_clk_n) - ); - - // ------------------------------------------------------------------------- - // IDELAYCTRL - // ------------------------------------------------------------------------- - (* IODELAY_GROUP = "rgmii_idelay_group" *) - IDELAYCTRL IDELAYCTRL_inst ( - .RDY (), - .REFCLK (sys_clk), - .RST (1'b0) - ); - - // ------------------------------------------------------------------------- - // Generated clocks for controller - // Need to create this IP in Vivado: - // input : 200 MHz - // output0: 130 MHz - // output1: 65 MHz - // ------------------------------------------------------------------------- - wire dac_clk; - wire adc_clk; - wire clk_wiz_locked; - - clk_wiz_ctrl_inst clk_wiz_ctrl_inst ( - .clk_in1 (sys_clk), - .reset (~rst_n), - .clk_out1 (dac_clk), // 130 MHz - .clk_out2 (adc_clk), // 65 MHz - .locked (clk_wiz_locked) - ); - - // ------------------------------------------------------------------------- - // GMII <-> RGMII conversion - // ------------------------------------------------------------------------- - util_gmii_to_rgmii util_gmii_to_rgmii_m0 ( - .reset (1'b0), - .rgmii_td (rgmii_txd), - .rgmii_tx_ctl (rgmii_txctl), - .rgmii_txc (rgmii_txc), - .rgmii_rd (rgmii_rxd), - .rgmii_rx_ctl (rgmii_rxctl), - .gmii_rx_clk (gmii_rx_clk), - .gmii_txd (e_txd), - .gmii_tx_en (e_tx_en), - .gmii_tx_er (1'b0), - .gmii_tx_clk (gmii_tx_clk), - .gmii_crs (gmii_crs), - .gmii_col (gmii_col), - .gmii_rxd (gmii_rxd_i), - .rgmii_rxc (rgmii_rxc), - .gmii_rx_dv (gmii_rx_dv), - .gmii_rx_er (gmii_rx_er), - .speed_selection (2'b10), - .duplex_mode (duplex_mode) - ); - - // ------------------------------------------------------------------------- - // GMII arbitration / adaptation - // ------------------------------------------------------------------------- - gmii_arbi arbi_inst ( - .clk (gmii_tx_clk), - .rst_n (rst_n), - .speed (2'b10), - .link (1'b1), - .pack_total_len (pack_total_len), - .e_rst_n (e_rst_n), - .gmii_rx_dv (gmii_rx_dv), - .gmii_rxd (gmii_rxd_i), - .gmii_tx_en (gmii_tx_en), - .gmii_txd (gmii_txd), - .e_rx_dv (e_rx_dv), - .e_rxd (e_rxd), - .e_tx_en (e_tx_en), - .e_txd (e_txd) - ); - - // ------------------------------------------------------------------------- - // axis_mac interface - // RX stream from Ethernet goes into controller - // TX stream is unused for now - // ------------------------------------------------------------------------- - (* MARK_DEBUG="true" *) logic req_ready; - (* MARK_DEBUG="true" *) logic send_req; - - (* MARK_DEBUG="true" *) logic [7:0] s_axis_tx_tdata; - (* MARK_DEBUG="true" *) logic s_axis_tx_tvalid; - (* MARK_DEBUG="true" *) logic s_axis_tx_tready; - (* MARK_DEBUG="true" *) logic s_axis_tx_tlast; - - (* MARK_DEBUG="true" *) wire [7:0] m_axis_rx_tdata; - (* MARK_DEBUG="true" *) wire m_axis_rx_tvalid; - (* MARK_DEBUG="true" *) wire m_axis_rx_tlast; - (* MARK_DEBUG="true" *) wire m_axis_rx_tready; - - - axis_mac axis_mac0 ( - .gmii_tx_clk (gmii_tx_clk), - .gmii_rx_clk (gmii_rx_clk), - .rst_n (e_rst_n), - - .gmii_rx_dv (e_rx_dv), - .gmii_rxd (e_rxd), - .gmii_tx_en (gmii_tx_en), - .gmii_txd (gmii_txd), - - .send_req (send_req), - .data_length (PACKET_SIZE), - .req_ready (req_ready), - - .s_axis_tx_tdata (s_axis_tx_tdata), - .s_axis_tx_tvalid (s_axis_tx_tvalid), - .s_axis_tx_tready (s_axis_tx_tready), - .s_axis_tx_tlast (s_axis_tx_tlast), - - .m_axis_rx_tdata (m_axis_rx_tdata), - .m_axis_rx_tvalid (m_axis_rx_tvalid), - .m_axis_rx_tready (m_axis_rx_tready), - .m_axis_rx_tlast (m_axis_rx_tlast) - ); - - // PHY reset helper from your original example - reset reset_m0 ( - .clk (sys_clk), - .key1 (rst_n), - .rst_n (e_reset) - ); - - // MDIO lines are not driven here yet - assign e_mdc = 1'b0; - assign e_mdio = 1'bz; - - // ------------------------------------------------------------------------- - // Controller reset - // Use both external reset and clk_wiz lock - // ------------------------------------------------------------------------- - wire ctrl_rst_n = rst_n & clk_wiz_locked; - - - (* MARK_DEBUG="true" *) logic finish; - - // Controller outputs to debug - (* MARK_DEBUG="true" *) wire [31:0] dac_pulse_width; - (* MARK_DEBUG="true" *) wire [31:0] dac_pulse_period; - (* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height; - (* MARK_DEBUG="true" *) wire [15:0] dac_pulse_num; - - (* MARK_DEBUG="true" *) wire [31:0] adc_pulse_period; - (* MARK_DEBUG="true" *) wire [15:0] adc_pulse_num; - - (* MARK_DEBUG="true" *) wire dac_start; - (* MARK_DEBUG="true" *) wire adc_start; - (* MARK_DEBUG="true" *) wire dac_rst; - (* MARK_DEBUG="true" *) wire adc_rst; - - - // ------------------------------------------------------------------------- - // Controller - // ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side - // ------------------------------------------------------------------------- - control #( - .DAC_DATA_WIDTH(DAC_DATA_WIDTH) - ) udp_ctrl_inst ( - .eth_clk_in (gmii_rx_clk), - .dac_clk_in (dac_clk), - .adc_clk_in (adc_clk), - .rst_n (ctrl_rst_n), - - .s_axis_tdata (m_axis_rx_tdata), - .s_axis_tvalid (m_axis_rx_tvalid), - .s_axis_tready (m_axis_rx_tready), - .s_axis_tlast (m_axis_rx_tlast), - - .finish (finish), - - .dac_pulse_width (dac_pulse_width), - .dac_pulse_period (dac_pulse_period), - .dac_pulse_height (dac_pulse_height), - .dac_pulse_num (dac_pulse_num), - - .adc_pulse_period (adc_pulse_period), - .adc_pulse_num (adc_pulse_num), - - .dac_start (dac_start), - .adc_start (adc_start), - - .dac_rst (dac_rst), - .adc_rst (adc_rst) - ); - - // ------------------------------------------------------------------------- - // DAC - // ------------------------------------------------------------------------- - - (* MARK_DEBUG="true" *) logic sample_req; - (* MARK_DEBUG="true" *) logic sample_req_sync1; - (* MARK_DEBUG="true" *) logic sample_req_sync2; - (* MARK_DEBUG="true" *) logic sample_req_sync3; - - (* MARK_DEBUG="true" *) logic sample_done; - (* MARK_DEBUG="true" *) logic sample_done_sync1; - (* MARK_DEBUG="true" *) logic sample_done_sync2; - (* MARK_DEBUG="true" *) logic sample_done_sync3; - - //------------------------------------------------------------ - // DAC -> ADC CDC - //------------------------------------------------------------ - always_ff @(posedge adc_clk or posedge adc_rst) begin - if (adc_rst) begin - sample_req <= 1'b0; - sample_req_sync2 <= 1'b0; - sample_req_sync3 <= 1'b0; - end - else begin - sample_req_sync2 <= sample_req_sync1; - sample_req_sync3 <= sample_req_sync2; - sample_req <= sample_req_sync3; - end - end - - //------------------------------------------------------------ - // ADC -> DAC CDC - //------------------------------------------------------------ - always_ff @(posedge dac_clk or posedge dac_rst) begin - if (dac_rst) begin - sample_done <= 1'b0; - sample_done_sync2 <= 1'b0; - sample_done_sync3 <= 1'b0; - end - else begin - sample_done_sync2 <= sample_done_sync1; - sample_done_sync3 <= sample_done_sync2; - sample_done <= sample_done_sync3; - end - end - - //------------------------------------------------------------ - // Generator - //------------------------------------------------------------ - - generator #( - .DATA_WIDTH(DAC_DATA_WIDTH) - ) generator_inst ( - .clk_in(dac_clk), - .rst(dac_rst), - .start(dac_start), - .pulse_width(dac_pulse_width), - .pulse_period(dac_pulse_period), - .pulse_height(dac_pulse_height), - .pulse_num(dac_pulse_num), - .pulse(p2_wrt), - .pulse_height_out(p2_data), - .sample_done(sample_done), - .sample_req(sample_req_sync1) - ); - - // adc clk mgt - wire ch2_clk_oddr; - - ODDR #( - .DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'b0), - .SRTYPE("SYNC") - ) ODDR_ch2_clk ( - .Q (ch2_clk_oddr), - .C (adc_clk), - .CE(1'b1), - .D1(1'b1), - .D2(1'b0), - .R (1'b0), - .S (1'b0) - ); - - OBUF OBUF_ch2_clk ( - .I(ch2_clk_oddr), - .O(ch2_clk) - ); - -// ------------------------------------------------------------------------- - // ADC - // ------------------------------------------------------------------------- - - (* MARK_DEBUG="true" *) logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] accum_m_axis_tdata; - (* MARK_DEBUG="true" *) logic acum_m_axis_tvalid; - - sampler - #( - .DATA_WIDTH(ADC_DATA_WIDTH), - .PACK_FACTOR(PACK_FACTOR), - .PROCESS_MODE(PROCESS_MODE) - ) - sampler_dut - ( - .clk_in(adc_clk), - .rst(adc_rst), - .data_in(ch2_data), - .out_of_range(ch2_otr), - .m_axis_tdata(accum_m_axis_tdata), - .m_axis_tvalid(acum_m_axis_tvalid), - .smp_num(adc_pulse_period), - .sample_req(sample_req), - .sample_done(sample_done_sync1) - ); - - // ------------------------------------------------------------------------- - // Accumulator - // ------------------------------------------------------------------------- - - accumulator_top - #( - .DATA_WIDTH(ADC_DATA_WIDTH), - .ACCUM_WIDTH(ACCUM_WIDTH), - .N_MAX(N_MAX), - .WINDOW_SIZE(WINDOW_SIZE), - .PACKET_SIZE(PACKET_SIZE) - ) - accumulator_top_dut - ( - .clk_in(adc_clk), - .rst(adc_rst), - .s_axis_tdata(accum_m_axis_tdata), - .s_axis_tvalid(acum_m_axis_tvalid), - .start(adc_start), - .smp_num(adc_pulse_period), - .seq_num(adc_pulse_num), - - .eth_clk_in(gmii_tx_clk), - .req_ready(req_ready), - .send_req(send_req), - .m_axis_tdata(s_axis_tx_tdata), - .m_axis_tvalid(s_axis_tx_tvalid), - .m_axis_tready(s_axis_tx_tready), - .m_axis_tlast(s_axis_tx_tlast), - - .finish(finish) - ); - - - // ------------------------------------------------------------------------- - // Simple LED status - // ------------------------------------------------------------------------- - assign led[0] = clk_wiz_locked; - assign led[1] = m_axis_rx_tvalid; - assign led[2] = dac_start; - assign led[3] = debug_dac; - -endmodule \ No newline at end of file diff --git a/designs/reflectometer/Makefile b/designs/reflectometer_base/Makefile similarity index 95% rename from designs/reflectometer/Makefile rename to designs/reflectometer_base/Makefile index 076d5b6..1c3fe92 100644 --- a/designs/reflectometer/Makefile +++ b/designs/reflectometer_base/Makefile @@ -7,7 +7,7 @@ # # FPGA settings -FPGA_PART = xc7a35tfgg484-1 +FPGA_PART = xc7a100tfgg484-2 FPGA_TOP = reflectometer_top FPGA_ARCH = artix7 @@ -22,7 +22,7 @@ SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv XCI_FILES = $(sort $(shell find ../../rtl/ethernet-udp/src -type f -name '*.xci')) XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci')) -XDC_FILES += ../../constraints/ax7a035b.xdc +XDC_FILES += ../../constraints/ax7102.xdc XDC_FILES += debug.xdc diff --git a/designs/reflectometer_base/debug.xdc b/designs/reflectometer_base/debug.xdc new file mode 100644 index 0000000..1e08ec3 --- /dev/null +++ b/designs/reflectometer_base/debug.xdc @@ -0,0 +1 @@ +set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst] diff --git a/designs/reflectometer/ip/clk_wiz_ctrl_inst.xci b/designs/reflectometer_base/ip/clk_wiz_ctrl_inst.xci similarity index 100% rename from designs/reflectometer/ip/clk_wiz_ctrl_inst.xci rename to designs/reflectometer_base/ip/clk_wiz_ctrl_inst.xci diff --git a/designs/reflectometer_without_eth/reflectometer.sv b/designs/reflectometer_base/reflectometer.sv similarity index 92% rename from designs/reflectometer_without_eth/reflectometer.sv rename to designs/reflectometer_base/reflectometer.sv index 2659afa..68f729c 100644 --- a/designs/reflectometer_without_eth/reflectometer.sv +++ b/designs/reflectometer_base/reflectometer.sv @@ -10,8 +10,7 @@ module reflectometer_top #( parameter WINDOW_SIZE = 65, parameter PACKET_SIZE = 1024 )( - input sys_clk_p, - input sys_clk_n, + input sys_clk, input rst_n, output [3:0] led, @@ -36,6 +35,7 @@ module reflectometer_top #( // DAC + output wire p2_clk, (* MARK_DEBUG="true" *) output wire [DAC_DATA_WIDTH-1:0] p2_data, (* MARK_DEBUG="true" *) output wire p2_wrt, @@ -45,20 +45,6 @@ module reflectometer_top #( input ch2_otr ); - // temp - - wire p2_wrt; - wire [13:0] p2_data; - - - // ------------------------------------------------------------------------- - // System clock buffer (200 MHz differential input) - // ------------------------------------------------------------------------- - IBUFDS sys_clk_ibufgds ( - .O (sys_clk), - .I (sys_clk_p), - .IB (sys_clk_n) - ); // ------------------------------------------------------------------------- // IDELAYCTRL @@ -94,9 +80,6 @@ module reflectometer_top #( // RX stream from Ethernet goes into controller // TX stream is unused for now // ------------------------------------------------------------------------- - (* MARK_DEBUG="true" *) logic req_ready; - (* MARK_DEBUG="true" *) logic send_req; - // ------------------------------------------------------------------------- @@ -223,6 +206,48 @@ module reflectometer_top #( .sample_req(sample_req_sync1) ); + wire ch2_clk_oddr; + + ODDR #( + .DDR_CLK_EDGE("SAME_EDGE"), + .INIT(1'b0), + .SRTYPE("SYNC") + ) ODDR_ch2_clk ( + .Q (ch2_clk_oddr), + .C (adc_clk), + .CE(1'b1), + .D1(1'b1), + .D2(1'b0), + .R (1'b0), + .S (1'b0) + ); + + OBUF OBUF_ch2_clk ( + .I(ch2_clk_oddr), + .O(ch2_clk) + ); + + wire p2_clk_oddr; + + ODDR #( + .DDR_CLK_EDGE("SAME_EDGE"), + .INIT(1'b0), + .SRTYPE("SYNC") + ) ODDR_p2_clk ( + .Q (p2_clk_oddr), + .C (dac_clk), + .CE(1'b1), + .D1(1'b1), + .D2(1'b0), + .R (1'b0), + .S (1'b0) + ); + + OBUF OBUF_p2_clk ( + .I(p2_clk_oddr), + .O(p2_clk) + ); + // ------------------------------------------------------------------------- // ADC // ------------------------------------------------------------------------- diff --git a/designs/reflectometer_prototype/Makefile b/designs/reflectometer_prototype/Makefile new file mode 100644 index 0000000..7836070 --- /dev/null +++ b/designs/reflectometer_prototype/Makefile @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xc7a100tfgg484-2 +FPGA_TOP = prototype_top +FPGA_ARCH = artix7 + +RTL_DIR = ../../rtl + + +include ../../scripts/vivado.mk + +SYN_FILES += prototype.sv +SYN_FILES += ../reflectometer_base/reflectometer.sv +SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \))) + +XCI_FILES = $(sort $(shell find ../../rtl/ethernet-udp/src -type f -name '*.xci')) +XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci')) + +XDC_FILES += ../../constraints/ax7102.xdc +XDC_FILES += debug.xdc + + + +program: $(PROJECT).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit + echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; diff --git a/designs/reflectometer/README.md b/designs/reflectometer_prototype/README.md similarity index 100% rename from designs/reflectometer/README.md rename to designs/reflectometer_prototype/README.md diff --git a/designs/reflectometer/debug.xdc b/designs/reflectometer_prototype/debug.xdc similarity index 52% rename from designs/reflectometer/debug.xdc rename to designs/reflectometer_prototype/debug.xdc index f47758d..629b711 100644 --- a/designs/reflectometer/debug.xdc +++ b/designs/reflectometer_prototype/debug.xdc @@ -1,203 +1,238 @@ -set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst] +set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rx_clk] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst] +connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]] +connect_debug_port u_ila_0/probe0 [get_nets [list {accumulator_top_dut/output_async_fifo/wr_state[0]} {accumulator_top_dut/output_async_fifo/wr_state[1]} {accumulator_top_dut/output_async_fifo/wr_state[2]}]] +connect_debug_port u_ila_0/probe1 [get_nets [list {sampler_dut/smp_num_reg[0]} {sampler_dut/smp_num_reg[1]} {sampler_dut/smp_num_reg[2]} {sampler_dut/smp_num_reg[3]} {sampler_dut/smp_num_reg[4]} {sampler_dut/smp_num_reg[5]} {sampler_dut/smp_num_reg[6]} {sampler_dut/smp_num_reg[7]} {sampler_dut/smp_num_reg[8]} {sampler_dut/smp_num_reg[9]} {sampler_dut/smp_num_reg[10]} {sampler_dut/smp_num_reg[11]} {sampler_dut/smp_num_reg[12]} {sampler_dut/smp_num_reg[13]} {sampler_dut/smp_num_reg[14]} {sampler_dut/smp_num_reg[15]} {sampler_dut/smp_num_reg[16]} {sampler_dut/smp_num_reg[17]} {sampler_dut/smp_num_reg[18]} {sampler_dut/smp_num_reg[19]} {sampler_dut/smp_num_reg[20]} {sampler_dut/smp_num_reg[21]} {sampler_dut/smp_num_reg[22]} {sampler_dut/smp_num_reg[23]} {sampler_dut/smp_num_reg[24]} {sampler_dut/smp_num_reg[25]} {sampler_dut/smp_num_reg[26]} {sampler_dut/smp_num_reg[27]} {sampler_dut/smp_num_reg[28]} {sampler_dut/smp_num_reg[29]} {sampler_dut/smp_num_reg[30]} {sampler_dut/smp_num_reg[31]}]] +connect_debug_port u_ila_0/probe2 [get_nets [list {adc_pulse_num[0]} {adc_pulse_num[1]} {adc_pulse_num[2]} {adc_pulse_num[3]} {adc_pulse_num[4]} {adc_pulse_num[5]} {adc_pulse_num[6]} {adc_pulse_num[7]} {adc_pulse_num[8]} {adc_pulse_num[9]} {adc_pulse_num[10]} {adc_pulse_num[11]} {adc_pulse_num[12]} {adc_pulse_num[13]} {adc_pulse_num[14]} {adc_pulse_num[15]}]] +connect_debug_port u_ila_0/probe4 [get_nets [list {accum_m_axis_tdata[0]} {accum_m_axis_tdata[1]} {accum_m_axis_tdata[2]} {accum_m_axis_tdata[3]} {accum_m_axis_tdata[4]} {accum_m_axis_tdata[5]} {accum_m_axis_tdata[6]} {accum_m_axis_tdata[7]} {accum_m_axis_tdata[8]} {accum_m_axis_tdata[9]} {accum_m_axis_tdata[10]} {accum_m_axis_tdata[11]}]] +connect_debug_port u_ila_0/probe5 [get_nets [list {sampler_dut/cnt_smp_num[0]} {sampler_dut/cnt_smp_num[1]} {sampler_dut/cnt_smp_num[2]} {sampler_dut/cnt_smp_num[3]} {sampler_dut/cnt_smp_num[4]} {sampler_dut/cnt_smp_num[5]} {sampler_dut/cnt_smp_num[6]} {sampler_dut/cnt_smp_num[7]} {sampler_dut/cnt_smp_num[8]} {sampler_dut/cnt_smp_num[9]} {sampler_dut/cnt_smp_num[10]} {sampler_dut/cnt_smp_num[11]} {sampler_dut/cnt_smp_num[12]} {sampler_dut/cnt_smp_num[13]} {sampler_dut/cnt_smp_num[14]} {sampler_dut/cnt_smp_num[15]} {sampler_dut/cnt_smp_num[16]} {sampler_dut/cnt_smp_num[17]} {sampler_dut/cnt_smp_num[18]} {sampler_dut/cnt_smp_num[19]} {sampler_dut/cnt_smp_num[20]} {sampler_dut/cnt_smp_num[21]} {sampler_dut/cnt_smp_num[22]} {sampler_dut/cnt_smp_num[23]} {sampler_dut/cnt_smp_num[24]} {sampler_dut/cnt_smp_num[25]} {sampler_dut/cnt_smp_num[26]} {sampler_dut/cnt_smp_num[27]} {sampler_dut/cnt_smp_num[28]} {sampler_dut/cnt_smp_num[29]} {sampler_dut/cnt_smp_num[30]} {sampler_dut/cnt_smp_num[31]}]] +connect_debug_port u_ila_0/probe6 [get_nets [list {sampler_dut/data_converted[0]} {sampler_dut/data_converted[1]} {sampler_dut/data_converted[2]} {sampler_dut/data_converted[3]} {sampler_dut/data_converted[4]} {sampler_dut/data_converted[5]} {sampler_dut/data_converted[6]} {sampler_dut/data_converted[7]} {sampler_dut/data_converted[8]} {sampler_dut/data_converted[9]} {sampler_dut/data_converted[10]} {sampler_dut/data_converted[11]}]] +connect_debug_port u_ila_0/probe7 [get_nets [list {adc_pulse_period[0]} {adc_pulse_period[1]} {adc_pulse_period[2]} {adc_pulse_period[3]} {adc_pulse_period[4]} {adc_pulse_period[5]} {adc_pulse_period[6]} {adc_pulse_period[7]} {adc_pulse_period[8]} {adc_pulse_period[9]} {adc_pulse_period[10]} {adc_pulse_period[11]} {adc_pulse_period[12]} {adc_pulse_period[13]} {adc_pulse_period[14]} {adc_pulse_period[15]} {adc_pulse_period[16]} {adc_pulse_period[17]} {adc_pulse_period[18]} {adc_pulse_period[19]} {adc_pulse_period[20]} {adc_pulse_period[21]} {adc_pulse_period[22]} {adc_pulse_period[23]} {adc_pulse_period[24]} {adc_pulse_period[25]} {adc_pulse_period[26]} {adc_pulse_period[27]} {adc_pulse_period[28]} {adc_pulse_period[29]} {adc_pulse_period[30]} {adc_pulse_period[31]}]] +connect_debug_port u_ila_0/probe8 [get_nets [list {accumulator_top_dut/accum_main/wr_state[0]} {accumulator_top_dut/accum_main/wr_state[1]} {accumulator_top_dut/accum_main/wr_state[2]} {accumulator_top_dut/accum_main/wr_state[3]}]] +connect_debug_port u_ila_0/probe9 [get_nets [list {accumulator_top_dut/accum_main/adder_dut/cnt[0]} {accumulator_top_dut/accum_main/adder_dut/cnt[1]} {accumulator_top_dut/accum_main/adder_dut/cnt[2]} {accumulator_top_dut/accum_main/adder_dut/cnt[3]} {accumulator_top_dut/accum_main/adder_dut/cnt[4]} {accumulator_top_dut/accum_main/adder_dut/cnt[5]} {accumulator_top_dut/accum_main/adder_dut/cnt[6]} {accumulator_top_dut/accum_main/adder_dut/cnt[7]} {accumulator_top_dut/accum_main/adder_dut/cnt[8]} {accumulator_top_dut/accum_main/adder_dut/cnt[9]} {accumulator_top_dut/accum_main/adder_dut/cnt[10]} {accumulator_top_dut/accum_main/adder_dut/cnt[11]} {accumulator_top_dut/accum_main/adder_dut/cnt[12]} {accumulator_top_dut/accum_main/adder_dut/cnt[13]} {accumulator_top_dut/accum_main/adder_dut/cnt[14]} {accumulator_top_dut/accum_main/adder_dut/cnt[15]}]] +connect_debug_port u_ila_0/probe10 [get_nets [list acum_m_axis_tvalid]] +connect_debug_port u_ila_0/probe11 [get_nets [list adc_rst]] +connect_debug_port u_ila_0/probe12 [get_nets [list adc_start]] +connect_debug_port u_ila_0/probe13 [get_nets [list sampler_dut/enable]] +connect_debug_port u_ila_0/probe14 [get_nets [list finish]] +connect_debug_port u_ila_0/probe15 [get_nets [list sampler_dut/out_of_range_reg]] +connect_debug_port u_ila_0/probe16 [get_nets [list sample_req]] +connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]] +connect_debug_port u_ila_1/probe0 [get_nets [list {generator_inst/pulse_num_reg[0]} {generator_inst/pulse_num_reg[1]} {generator_inst/pulse_num_reg[2]} {generator_inst/pulse_num_reg[3]} {generator_inst/pulse_num_reg[4]} {generator_inst/pulse_num_reg[5]} {generator_inst/pulse_num_reg[6]} {generator_inst/pulse_num_reg[7]} {generator_inst/pulse_num_reg[8]} {generator_inst/pulse_num_reg[9]} {generator_inst/pulse_num_reg[10]} {generator_inst/pulse_num_reg[11]} {generator_inst/pulse_num_reg[12]} {generator_inst/pulse_num_reg[13]} {generator_inst/pulse_num_reg[14]} {generator_inst/pulse_num_reg[15]}]] +connect_debug_port u_ila_1/probe1 [get_nets [list {dac_pulse_num[0]} {dac_pulse_num[1]} {dac_pulse_num[2]} {dac_pulse_num[3]} {dac_pulse_num[4]} {dac_pulse_num[5]} {dac_pulse_num[6]} {dac_pulse_num[7]} {dac_pulse_num[8]} {dac_pulse_num[9]} {dac_pulse_num[10]} {dac_pulse_num[11]} {dac_pulse_num[12]} {dac_pulse_num[13]} {dac_pulse_num[14]} {dac_pulse_num[15]}]] +connect_debug_port u_ila_1/probe2 [get_nets [list {dac_pulse_period[0]} {dac_pulse_period[1]} {dac_pulse_period[2]} {dac_pulse_period[3]} {dac_pulse_period[4]} {dac_pulse_period[5]} {dac_pulse_period[6]} {dac_pulse_period[7]} {dac_pulse_period[8]} {dac_pulse_period[9]} {dac_pulse_period[10]} {dac_pulse_period[11]} {dac_pulse_period[12]} {dac_pulse_period[13]} {dac_pulse_period[14]} {dac_pulse_period[15]} {dac_pulse_period[16]} {dac_pulse_period[17]} {dac_pulse_period[18]} {dac_pulse_period[19]} {dac_pulse_period[20]} {dac_pulse_period[21]} {dac_pulse_period[22]} {dac_pulse_period[23]} {dac_pulse_period[24]} {dac_pulse_period[25]} {dac_pulse_period[26]} {dac_pulse_period[27]} {dac_pulse_period[28]} {dac_pulse_period[29]} {dac_pulse_period[30]} {dac_pulse_period[31]}]] +connect_debug_port u_ila_1/probe3 [get_nets [list {dac_pulse_width[0]} {dac_pulse_width[1]} {dac_pulse_width[2]} {dac_pulse_width[3]} {dac_pulse_width[4]} {dac_pulse_width[5]} {dac_pulse_width[6]} {dac_pulse_width[7]} {dac_pulse_width[8]} {dac_pulse_width[9]} {dac_pulse_width[10]} {dac_pulse_width[11]} {dac_pulse_width[12]} {dac_pulse_width[13]} {dac_pulse_width[14]} {dac_pulse_width[15]} {dac_pulse_width[16]} {dac_pulse_width[17]} {dac_pulse_width[18]} {dac_pulse_width[19]} {dac_pulse_width[20]} {dac_pulse_width[21]} {dac_pulse_width[22]} {dac_pulse_width[23]} {dac_pulse_width[24]} {dac_pulse_width[25]} {dac_pulse_width[26]} {dac_pulse_width[27]} {dac_pulse_width[28]} {dac_pulse_width[29]} {dac_pulse_width[30]} {dac_pulse_width[31]}]] +connect_debug_port u_ila_1/probe4 [get_nets [list {generator_inst/cnt_pulse_num[0]} {generator_inst/cnt_pulse_num[1]} {generator_inst/cnt_pulse_num[2]} {generator_inst/cnt_pulse_num[3]} {generator_inst/cnt_pulse_num[4]} {generator_inst/cnt_pulse_num[5]} {generator_inst/cnt_pulse_num[6]} {generator_inst/cnt_pulse_num[7]} {generator_inst/cnt_pulse_num[8]} {generator_inst/cnt_pulse_num[9]} {generator_inst/cnt_pulse_num[10]} {generator_inst/cnt_pulse_num[11]} {generator_inst/cnt_pulse_num[12]} {generator_inst/cnt_pulse_num[13]} {generator_inst/cnt_pulse_num[14]} {generator_inst/cnt_pulse_num[15]}]] +connect_debug_port u_ila_1/probe5 [get_nets [list {generator_inst/pulse_width_reg[0]} {generator_inst/pulse_width_reg[1]} {generator_inst/pulse_width_reg[2]} {generator_inst/pulse_width_reg[3]} {generator_inst/pulse_width_reg[4]} {generator_inst/pulse_width_reg[5]} {generator_inst/pulse_width_reg[6]} {generator_inst/pulse_width_reg[7]} {generator_inst/pulse_width_reg[8]} {generator_inst/pulse_width_reg[9]} {generator_inst/pulse_width_reg[10]} {generator_inst/pulse_width_reg[11]} {generator_inst/pulse_width_reg[12]} {generator_inst/pulse_width_reg[13]} {generator_inst/pulse_width_reg[14]} {generator_inst/pulse_width_reg[15]} {generator_inst/pulse_width_reg[16]} {generator_inst/pulse_width_reg[17]} {generator_inst/pulse_width_reg[18]} {generator_inst/pulse_width_reg[19]} {generator_inst/pulse_width_reg[20]} {generator_inst/pulse_width_reg[21]} {generator_inst/pulse_width_reg[22]} {generator_inst/pulse_width_reg[23]} {generator_inst/pulse_width_reg[24]} {generator_inst/pulse_width_reg[25]} {generator_inst/pulse_width_reg[26]} {generator_inst/pulse_width_reg[27]} {generator_inst/pulse_width_reg[28]} {generator_inst/pulse_width_reg[29]} {generator_inst/pulse_width_reg[30]} {generator_inst/pulse_width_reg[31]}]] +connect_debug_port u_ila_1/probe6 [get_nets [list {generator_inst/pulse_period_reg[0]} {generator_inst/pulse_period_reg[1]} {generator_inst/pulse_period_reg[2]} {generator_inst/pulse_period_reg[3]} {generator_inst/pulse_period_reg[4]} {generator_inst/pulse_period_reg[5]} {generator_inst/pulse_period_reg[6]} {generator_inst/pulse_period_reg[7]} {generator_inst/pulse_period_reg[8]} {generator_inst/pulse_period_reg[9]} {generator_inst/pulse_period_reg[10]} {generator_inst/pulse_period_reg[11]} {generator_inst/pulse_period_reg[12]} {generator_inst/pulse_period_reg[13]} {generator_inst/pulse_period_reg[14]} {generator_inst/pulse_period_reg[15]} {generator_inst/pulse_period_reg[16]} {generator_inst/pulse_period_reg[17]} {generator_inst/pulse_period_reg[18]} {generator_inst/pulse_period_reg[19]} {generator_inst/pulse_period_reg[20]} {generator_inst/pulse_period_reg[21]} {generator_inst/pulse_period_reg[22]} {generator_inst/pulse_period_reg[23]} {generator_inst/pulse_period_reg[24]} {generator_inst/pulse_period_reg[25]} {generator_inst/pulse_period_reg[26]} {generator_inst/pulse_period_reg[27]} {generator_inst/pulse_period_reg[28]} {generator_inst/pulse_period_reg[29]} {generator_inst/pulse_period_reg[30]} {generator_inst/pulse_period_reg[31]}]] +connect_debug_port u_ila_1/probe7 [get_nets [list {generator_inst/cnt_period[0]} {generator_inst/cnt_period[1]} {generator_inst/cnt_period[2]} {generator_inst/cnt_period[3]} {generator_inst/cnt_period[4]} {generator_inst/cnt_period[5]} {generator_inst/cnt_period[6]} {generator_inst/cnt_period[7]} {generator_inst/cnt_period[8]} {generator_inst/cnt_period[9]} {generator_inst/cnt_period[10]} {generator_inst/cnt_period[11]} {generator_inst/cnt_period[12]} {generator_inst/cnt_period[13]} {generator_inst/cnt_period[14]} {generator_inst/cnt_period[15]} {generator_inst/cnt_period[16]} {generator_inst/cnt_period[17]} {generator_inst/cnt_period[18]} {generator_inst/cnt_period[19]} {generator_inst/cnt_period[20]} {generator_inst/cnt_period[21]} {generator_inst/cnt_period[22]} {generator_inst/cnt_period[23]} {generator_inst/cnt_period[24]} {generator_inst/cnt_period[25]} {generator_inst/cnt_period[26]} {generator_inst/cnt_period[27]} {generator_inst/cnt_period[28]} {generator_inst/cnt_period[29]} {generator_inst/cnt_period[30]} {generator_inst/cnt_period[31]}]] +connect_debug_port u_ila_1/probe8 [get_nets [list dac_rst]] +connect_debug_port u_ila_1/probe9 [get_nets [list dac_start]] +connect_debug_port u_ila_1/probe10 [get_nets [list debug_dac_OBUF]] +connect_debug_port u_ila_1/probe11 [get_nets [list generator_inst/enable]] +connect_debug_port u_ila_1/probe12 [get_nets [list sample_done]] +connect_debug_port u_ila_2/clk [get_nets [list rgmii_rxc_IBUF_BUFG]] +connect_debug_port u_ila_2/probe0 [get_nets [list {accumulator_top_dut/output_async_fifo/rd_state[0]} {accumulator_top_dut/output_async_fifo/rd_state[1]} {accumulator_top_dut/output_async_fifo/rd_state[2]}]] +connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG] + create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] -set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] -set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] -set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] -connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]] +connect_debug_port u_ila_0/clk [get_nets [list reflectometer_inst/clk_wiz_ctrl_inst/inst/clk_out2]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -set_property port_width 3 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {accumulator_top_dut/output_async_fifo/wr_state[0]} {accumulator_top_dut/output_async_fifo/wr_state[1]} {accumulator_top_dut/output_async_fifo/wr_state[2]}]] +set_property port_width 4 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {reflectometer_inst/accumulator_top_dut/accum_main/wr_state[0]} {reflectometer_inst/accumulator_top_dut/accum_main/wr_state[1]} {reflectometer_inst/accumulator_top_dut/accum_main/wr_state[2]} {reflectometer_inst/accumulator_top_dut/accum_main/wr_state[3]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -set_property port_width 32 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {sampler_dut/smp_num_reg[0]} {sampler_dut/smp_num_reg[1]} {sampler_dut/smp_num_reg[2]} {sampler_dut/smp_num_reg[3]} {sampler_dut/smp_num_reg[4]} {sampler_dut/smp_num_reg[5]} {sampler_dut/smp_num_reg[6]} {sampler_dut/smp_num_reg[7]} {sampler_dut/smp_num_reg[8]} {sampler_dut/smp_num_reg[9]} {sampler_dut/smp_num_reg[10]} {sampler_dut/smp_num_reg[11]} {sampler_dut/smp_num_reg[12]} {sampler_dut/smp_num_reg[13]} {sampler_dut/smp_num_reg[14]} {sampler_dut/smp_num_reg[15]} {sampler_dut/smp_num_reg[16]} {sampler_dut/smp_num_reg[17]} {sampler_dut/smp_num_reg[18]} {sampler_dut/smp_num_reg[19]} {sampler_dut/smp_num_reg[20]} {sampler_dut/smp_num_reg[21]} {sampler_dut/smp_num_reg[22]} {sampler_dut/smp_num_reg[23]} {sampler_dut/smp_num_reg[24]} {sampler_dut/smp_num_reg[25]} {sampler_dut/smp_num_reg[26]} {sampler_dut/smp_num_reg[27]} {sampler_dut/smp_num_reg[28]} {sampler_dut/smp_num_reg[29]} {sampler_dut/smp_num_reg[30]} {sampler_dut/smp_num_reg[31]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {reflectometer_inst/accumulator_top_dut/output_async_fifo/wr_state[0]} {reflectometer_inst/accumulator_top_dut/output_async_fifo/wr_state[1]} {reflectometer_inst/accumulator_top_dut/output_async_fifo/wr_state[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -set_property port_width 16 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {adc_pulse_num[0]} {adc_pulse_num[1]} {adc_pulse_num[2]} {adc_pulse_num[3]} {adc_pulse_num[4]} {adc_pulse_num[5]} {adc_pulse_num[6]} {adc_pulse_num[7]} {adc_pulse_num[8]} {adc_pulse_num[9]} {adc_pulse_num[10]} {adc_pulse_num[11]} {adc_pulse_num[12]} {adc_pulse_num[13]} {adc_pulse_num[14]} {adc_pulse_num[15]}]] +set_property port_width 32 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {reflectometer_inst/sampler_dut/cnt_smp_num[0]} {reflectometer_inst/sampler_dut/cnt_smp_num[1]} {reflectometer_inst/sampler_dut/cnt_smp_num[2]} {reflectometer_inst/sampler_dut/cnt_smp_num[3]} {reflectometer_inst/sampler_dut/cnt_smp_num[4]} {reflectometer_inst/sampler_dut/cnt_smp_num[5]} {reflectometer_inst/sampler_dut/cnt_smp_num[6]} {reflectometer_inst/sampler_dut/cnt_smp_num[7]} {reflectometer_inst/sampler_dut/cnt_smp_num[8]} {reflectometer_inst/sampler_dut/cnt_smp_num[9]} {reflectometer_inst/sampler_dut/cnt_smp_num[10]} {reflectometer_inst/sampler_dut/cnt_smp_num[11]} {reflectometer_inst/sampler_dut/cnt_smp_num[12]} {reflectometer_inst/sampler_dut/cnt_smp_num[13]} {reflectometer_inst/sampler_dut/cnt_smp_num[14]} {reflectometer_inst/sampler_dut/cnt_smp_num[15]} {reflectometer_inst/sampler_dut/cnt_smp_num[16]} {reflectometer_inst/sampler_dut/cnt_smp_num[17]} {reflectometer_inst/sampler_dut/cnt_smp_num[18]} {reflectometer_inst/sampler_dut/cnt_smp_num[19]} {reflectometer_inst/sampler_dut/cnt_smp_num[20]} {reflectometer_inst/sampler_dut/cnt_smp_num[21]} {reflectometer_inst/sampler_dut/cnt_smp_num[22]} {reflectometer_inst/sampler_dut/cnt_smp_num[23]} {reflectometer_inst/sampler_dut/cnt_smp_num[24]} {reflectometer_inst/sampler_dut/cnt_smp_num[25]} {reflectometer_inst/sampler_dut/cnt_smp_num[26]} {reflectometer_inst/sampler_dut/cnt_smp_num[27]} {reflectometer_inst/sampler_dut/cnt_smp_num[28]} {reflectometer_inst/sampler_dut/cnt_smp_num[29]} {reflectometer_inst/sampler_dut/cnt_smp_num[30]} {reflectometer_inst/sampler_dut/cnt_smp_num[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] set_property port_width 12 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {ch2_data_IBUF[0]} {ch2_data_IBUF[1]} {ch2_data_IBUF[2]} {ch2_data_IBUF[3]} {ch2_data_IBUF[4]} {ch2_data_IBUF[5]} {ch2_data_IBUF[6]} {ch2_data_IBUF[7]} {ch2_data_IBUF[8]} {ch2_data_IBUF[9]} {ch2_data_IBUF[10]} {ch2_data_IBUF[11]}]] +connect_debug_port u_ila_0/probe3 [get_nets [list {reflectometer_inst/sampler_dut/data_converted[0]} {reflectometer_inst/sampler_dut/data_converted[1]} {reflectometer_inst/sampler_dut/data_converted[2]} {reflectometer_inst/sampler_dut/data_converted[3]} {reflectometer_inst/sampler_dut/data_converted[4]} {reflectometer_inst/sampler_dut/data_converted[5]} {reflectometer_inst/sampler_dut/data_converted[6]} {reflectometer_inst/sampler_dut/data_converted[7]} {reflectometer_inst/sampler_dut/data_converted[8]} {reflectometer_inst/sampler_dut/data_converted[9]} {reflectometer_inst/sampler_dut/data_converted[10]} {reflectometer_inst/sampler_dut/data_converted[11]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -set_property port_width 12 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {accum_m_axis_tdata[0]} {accum_m_axis_tdata[1]} {accum_m_axis_tdata[2]} {accum_m_axis_tdata[3]} {accum_m_axis_tdata[4]} {accum_m_axis_tdata[5]} {accum_m_axis_tdata[6]} {accum_m_axis_tdata[7]} {accum_m_axis_tdata[8]} {accum_m_axis_tdata[9]} {accum_m_axis_tdata[10]} {accum_m_axis_tdata[11]}]] +set_property port_width 32 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {reflectometer_inst/sampler_dut/smp_num_reg[0]} {reflectometer_inst/sampler_dut/smp_num_reg[1]} {reflectometer_inst/sampler_dut/smp_num_reg[2]} {reflectometer_inst/sampler_dut/smp_num_reg[3]} {reflectometer_inst/sampler_dut/smp_num_reg[4]} {reflectometer_inst/sampler_dut/smp_num_reg[5]} {reflectometer_inst/sampler_dut/smp_num_reg[6]} {reflectometer_inst/sampler_dut/smp_num_reg[7]} {reflectometer_inst/sampler_dut/smp_num_reg[8]} {reflectometer_inst/sampler_dut/smp_num_reg[9]} {reflectometer_inst/sampler_dut/smp_num_reg[10]} {reflectometer_inst/sampler_dut/smp_num_reg[11]} {reflectometer_inst/sampler_dut/smp_num_reg[12]} {reflectometer_inst/sampler_dut/smp_num_reg[13]} {reflectometer_inst/sampler_dut/smp_num_reg[14]} {reflectometer_inst/sampler_dut/smp_num_reg[15]} {reflectometer_inst/sampler_dut/smp_num_reg[16]} {reflectometer_inst/sampler_dut/smp_num_reg[17]} {reflectometer_inst/sampler_dut/smp_num_reg[18]} {reflectometer_inst/sampler_dut/smp_num_reg[19]} {reflectometer_inst/sampler_dut/smp_num_reg[20]} {reflectometer_inst/sampler_dut/smp_num_reg[21]} {reflectometer_inst/sampler_dut/smp_num_reg[22]} {reflectometer_inst/sampler_dut/smp_num_reg[23]} {reflectometer_inst/sampler_dut/smp_num_reg[24]} {reflectometer_inst/sampler_dut/smp_num_reg[25]} {reflectometer_inst/sampler_dut/smp_num_reg[26]} {reflectometer_inst/sampler_dut/smp_num_reg[27]} {reflectometer_inst/sampler_dut/smp_num_reg[28]} {reflectometer_inst/sampler_dut/smp_num_reg[29]} {reflectometer_inst/sampler_dut/smp_num_reg[30]} {reflectometer_inst/sampler_dut/smp_num_reg[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -set_property port_width 32 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {sampler_dut/cnt_smp_num[0]} {sampler_dut/cnt_smp_num[1]} {sampler_dut/cnt_smp_num[2]} {sampler_dut/cnt_smp_num[3]} {sampler_dut/cnt_smp_num[4]} {sampler_dut/cnt_smp_num[5]} {sampler_dut/cnt_smp_num[6]} {sampler_dut/cnt_smp_num[7]} {sampler_dut/cnt_smp_num[8]} {sampler_dut/cnt_smp_num[9]} {sampler_dut/cnt_smp_num[10]} {sampler_dut/cnt_smp_num[11]} {sampler_dut/cnt_smp_num[12]} {sampler_dut/cnt_smp_num[13]} {sampler_dut/cnt_smp_num[14]} {sampler_dut/cnt_smp_num[15]} {sampler_dut/cnt_smp_num[16]} {sampler_dut/cnt_smp_num[17]} {sampler_dut/cnt_smp_num[18]} {sampler_dut/cnt_smp_num[19]} {sampler_dut/cnt_smp_num[20]} {sampler_dut/cnt_smp_num[21]} {sampler_dut/cnt_smp_num[22]} {sampler_dut/cnt_smp_num[23]} {sampler_dut/cnt_smp_num[24]} {sampler_dut/cnt_smp_num[25]} {sampler_dut/cnt_smp_num[26]} {sampler_dut/cnt_smp_num[27]} {sampler_dut/cnt_smp_num[28]} {sampler_dut/cnt_smp_num[29]} {sampler_dut/cnt_smp_num[30]} {sampler_dut/cnt_smp_num[31]}]] +set_property port_width 12 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {reflectometer_inst/accum_m_axis_tdata[0]} {reflectometer_inst/accum_m_axis_tdata[1]} {reflectometer_inst/accum_m_axis_tdata[2]} {reflectometer_inst/accum_m_axis_tdata[3]} {reflectometer_inst/accum_m_axis_tdata[4]} {reflectometer_inst/accum_m_axis_tdata[5]} {reflectometer_inst/accum_m_axis_tdata[6]} {reflectometer_inst/accum_m_axis_tdata[7]} {reflectometer_inst/accum_m_axis_tdata[8]} {reflectometer_inst/accum_m_axis_tdata[9]} {reflectometer_inst/accum_m_axis_tdata[10]} {reflectometer_inst/accum_m_axis_tdata[11]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -set_property port_width 12 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {sampler_dut/data_converted[0]} {sampler_dut/data_converted[1]} {sampler_dut/data_converted[2]} {sampler_dut/data_converted[3]} {sampler_dut/data_converted[4]} {sampler_dut/data_converted[5]} {sampler_dut/data_converted[6]} {sampler_dut/data_converted[7]} {sampler_dut/data_converted[8]} {sampler_dut/data_converted[9]} {sampler_dut/data_converted[10]} {sampler_dut/data_converted[11]}]] +set_property port_width 16 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {reflectometer_inst/adc_pulse_num[0]} {reflectometer_inst/adc_pulse_num[1]} {reflectometer_inst/adc_pulse_num[2]} {reflectometer_inst/adc_pulse_num[3]} {reflectometer_inst/adc_pulse_num[4]} {reflectometer_inst/adc_pulse_num[5]} {reflectometer_inst/adc_pulse_num[6]} {reflectometer_inst/adc_pulse_num[7]} {reflectometer_inst/adc_pulse_num[8]} {reflectometer_inst/adc_pulse_num[9]} {reflectometer_inst/adc_pulse_num[10]} {reflectometer_inst/adc_pulse_num[11]} {reflectometer_inst/adc_pulse_num[12]} {reflectometer_inst/adc_pulse_num[13]} {reflectometer_inst/adc_pulse_num[14]} {reflectometer_inst/adc_pulse_num[15]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] set_property port_width 32 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list {adc_pulse_period[0]} {adc_pulse_period[1]} {adc_pulse_period[2]} {adc_pulse_period[3]} {adc_pulse_period[4]} {adc_pulse_period[5]} {adc_pulse_period[6]} {adc_pulse_period[7]} {adc_pulse_period[8]} {adc_pulse_period[9]} {adc_pulse_period[10]} {adc_pulse_period[11]} {adc_pulse_period[12]} {adc_pulse_period[13]} {adc_pulse_period[14]} {adc_pulse_period[15]} {adc_pulse_period[16]} {adc_pulse_period[17]} {adc_pulse_period[18]} {adc_pulse_period[19]} {adc_pulse_period[20]} {adc_pulse_period[21]} {adc_pulse_period[22]} {adc_pulse_period[23]} {adc_pulse_period[24]} {adc_pulse_period[25]} {adc_pulse_period[26]} {adc_pulse_period[27]} {adc_pulse_period[28]} {adc_pulse_period[29]} {adc_pulse_period[30]} {adc_pulse_period[31]}]] +connect_debug_port u_ila_0/probe7 [get_nets [list {reflectometer_inst/adc_pulse_period[0]} {reflectometer_inst/adc_pulse_period[1]} {reflectometer_inst/adc_pulse_period[2]} {reflectometer_inst/adc_pulse_period[3]} {reflectometer_inst/adc_pulse_period[4]} {reflectometer_inst/adc_pulse_period[5]} {reflectometer_inst/adc_pulse_period[6]} {reflectometer_inst/adc_pulse_period[7]} {reflectometer_inst/adc_pulse_period[8]} {reflectometer_inst/adc_pulse_period[9]} {reflectometer_inst/adc_pulse_period[10]} {reflectometer_inst/adc_pulse_period[11]} {reflectometer_inst/adc_pulse_period[12]} {reflectometer_inst/adc_pulse_period[13]} {reflectometer_inst/adc_pulse_period[14]} {reflectometer_inst/adc_pulse_period[15]} {reflectometer_inst/adc_pulse_period[16]} {reflectometer_inst/adc_pulse_period[17]} {reflectometer_inst/adc_pulse_period[18]} {reflectometer_inst/adc_pulse_period[19]} {reflectometer_inst/adc_pulse_period[20]} {reflectometer_inst/adc_pulse_period[21]} {reflectometer_inst/adc_pulse_period[22]} {reflectometer_inst/adc_pulse_period[23]} {reflectometer_inst/adc_pulse_period[24]} {reflectometer_inst/adc_pulse_period[25]} {reflectometer_inst/adc_pulse_period[26]} {reflectometer_inst/adc_pulse_period[27]} {reflectometer_inst/adc_pulse_period[28]} {reflectometer_inst/adc_pulse_period[29]} {reflectometer_inst/adc_pulse_period[30]} {reflectometer_inst/adc_pulse_period[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] -set_property port_width 4 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list {accumulator_top_dut/accum_main/wr_state[0]} {accumulator_top_dut/accum_main/wr_state[1]} {accumulator_top_dut/accum_main/wr_state[2]} {accumulator_top_dut/accum_main/wr_state[3]}]] +set_property port_width 12 [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list {ch2_data_IBUF[0]} {ch2_data_IBUF[1]} {ch2_data_IBUF[2]} {ch2_data_IBUF[3]} {ch2_data_IBUF[4]} {ch2_data_IBUF[5]} {ch2_data_IBUF[6]} {ch2_data_IBUF[7]} {ch2_data_IBUF[8]} {ch2_data_IBUF[9]} {ch2_data_IBUF[10]} {ch2_data_IBUF[11]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] -set_property port_width 16 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list {accumulator_top_dut/accum_main/adder_dut/cnt[0]} {accumulator_top_dut/accum_main/adder_dut/cnt[1]} {accumulator_top_dut/accum_main/adder_dut/cnt[2]} {accumulator_top_dut/accum_main/adder_dut/cnt[3]} {accumulator_top_dut/accum_main/adder_dut/cnt[4]} {accumulator_top_dut/accum_main/adder_dut/cnt[5]} {accumulator_top_dut/accum_main/adder_dut/cnt[6]} {accumulator_top_dut/accum_main/adder_dut/cnt[7]} {accumulator_top_dut/accum_main/adder_dut/cnt[8]} {accumulator_top_dut/accum_main/adder_dut/cnt[9]} {accumulator_top_dut/accum_main/adder_dut/cnt[10]} {accumulator_top_dut/accum_main/adder_dut/cnt[11]} {accumulator_top_dut/accum_main/adder_dut/cnt[12]} {accumulator_top_dut/accum_main/adder_dut/cnt[13]} {accumulator_top_dut/accum_main/adder_dut/cnt[14]} {accumulator_top_dut/accum_main/adder_dut/cnt[15]}]] +set_property port_width 1 [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list reflectometer_inst/acum_m_axis_tvalid]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] set_property port_width 1 [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list acum_m_axis_tvalid]] +connect_debug_port u_ila_0/probe10 [get_nets [list reflectometer_inst/adc_rst]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] set_property port_width 1 [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list adc_rst]] +connect_debug_port u_ila_0/probe11 [get_nets [list reflectometer_inst/adc_start]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] set_property port_width 1 [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list adc_start]] +connect_debug_port u_ila_0/probe12 [get_nets [list reflectometer_inst/sampler_dut/buffer_ready]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] set_property port_width 1 [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list sampler_dut/enable]] +connect_debug_port u_ila_0/probe13 [get_nets [list reflectometer_inst/sampler_dut/enable]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] set_property port_width 1 [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list finish]] +connect_debug_port u_ila_0/probe14 [get_nets [list reflectometer_inst/finish]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] set_property port_width 1 [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list sampler_dut/out_of_range_reg]] +connect_debug_port u_ila_0/probe15 [get_nets [list reflectometer_inst/sampler_dut/out_of_range_reg]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] set_property port_width 1 [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list sample_req]] +connect_debug_port u_ila_0/probe16 [get_nets [list reflectometer_inst/sample_req]] create_debug_core u_ila_1 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1] -set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_1] -set_property C_ADV_TRIGGER true [get_debug_cores u_ila_1] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1] set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1] -set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_1] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1] set_property C_TRIGIN_EN false [get_debug_cores u_ila_1] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1] set_property port_width 1 [get_debug_ports u_ila_1/clk] -connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]] +connect_debug_port u_ila_1/clk [get_nets [list reflectometer_inst/clk_wiz_ctrl_inst/inst/clk_out1]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0] -set_property port_width 16 [get_debug_ports u_ila_1/probe0] -connect_debug_port u_ila_1/probe0 [get_nets [list {generator_inst/pulse_num_reg[0]} {generator_inst/pulse_num_reg[1]} {generator_inst/pulse_num_reg[2]} {generator_inst/pulse_num_reg[3]} {generator_inst/pulse_num_reg[4]} {generator_inst/pulse_num_reg[5]} {generator_inst/pulse_num_reg[6]} {generator_inst/pulse_num_reg[7]} {generator_inst/pulse_num_reg[8]} {generator_inst/pulse_num_reg[9]} {generator_inst/pulse_num_reg[10]} {generator_inst/pulse_num_reg[11]} {generator_inst/pulse_num_reg[12]} {generator_inst/pulse_num_reg[13]} {generator_inst/pulse_num_reg[14]} {generator_inst/pulse_num_reg[15]}]] +set_property port_width 32 [get_debug_ports u_ila_1/probe0] +connect_debug_port u_ila_1/probe0 [get_nets [list {reflectometer_inst/generator_inst/cnt_period[0]} {reflectometer_inst/generator_inst/cnt_period[1]} {reflectometer_inst/generator_inst/cnt_period[2]} {reflectometer_inst/generator_inst/cnt_period[3]} {reflectometer_inst/generator_inst/cnt_period[4]} {reflectometer_inst/generator_inst/cnt_period[5]} {reflectometer_inst/generator_inst/cnt_period[6]} {reflectometer_inst/generator_inst/cnt_period[7]} {reflectometer_inst/generator_inst/cnt_period[8]} {reflectometer_inst/generator_inst/cnt_period[9]} {reflectometer_inst/generator_inst/cnt_period[10]} {reflectometer_inst/generator_inst/cnt_period[11]} {reflectometer_inst/generator_inst/cnt_period[12]} {reflectometer_inst/generator_inst/cnt_period[13]} {reflectometer_inst/generator_inst/cnt_period[14]} {reflectometer_inst/generator_inst/cnt_period[15]} {reflectometer_inst/generator_inst/cnt_period[16]} {reflectometer_inst/generator_inst/cnt_period[17]} {reflectometer_inst/generator_inst/cnt_period[18]} {reflectometer_inst/generator_inst/cnt_period[19]} {reflectometer_inst/generator_inst/cnt_period[20]} {reflectometer_inst/generator_inst/cnt_period[21]} {reflectometer_inst/generator_inst/cnt_period[22]} {reflectometer_inst/generator_inst/cnt_period[23]} {reflectometer_inst/generator_inst/cnt_period[24]} {reflectometer_inst/generator_inst/cnt_period[25]} {reflectometer_inst/generator_inst/cnt_period[26]} {reflectometer_inst/generator_inst/cnt_period[27]} {reflectometer_inst/generator_inst/cnt_period[28]} {reflectometer_inst/generator_inst/cnt_period[29]} {reflectometer_inst/generator_inst/cnt_period[30]} {reflectometer_inst/generator_inst/cnt_period[31]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1] set_property port_width 16 [get_debug_ports u_ila_1/probe1] -connect_debug_port u_ila_1/probe1 [get_nets [list {dac_pulse_num[0]} {dac_pulse_num[1]} {dac_pulse_num[2]} {dac_pulse_num[3]} {dac_pulse_num[4]} {dac_pulse_num[5]} {dac_pulse_num[6]} {dac_pulse_num[7]} {dac_pulse_num[8]} {dac_pulse_num[9]} {dac_pulse_num[10]} {dac_pulse_num[11]} {dac_pulse_num[12]} {dac_pulse_num[13]} {dac_pulse_num[14]} {dac_pulse_num[15]}]] +connect_debug_port u_ila_1/probe1 [get_nets [list {reflectometer_inst/generator_inst/cnt_pulse_num[0]} {reflectometer_inst/generator_inst/cnt_pulse_num[1]} {reflectometer_inst/generator_inst/cnt_pulse_num[2]} {reflectometer_inst/generator_inst/cnt_pulse_num[3]} {reflectometer_inst/generator_inst/cnt_pulse_num[4]} {reflectometer_inst/generator_inst/cnt_pulse_num[5]} {reflectometer_inst/generator_inst/cnt_pulse_num[6]} {reflectometer_inst/generator_inst/cnt_pulse_num[7]} {reflectometer_inst/generator_inst/cnt_pulse_num[8]} {reflectometer_inst/generator_inst/cnt_pulse_num[9]} {reflectometer_inst/generator_inst/cnt_pulse_num[10]} {reflectometer_inst/generator_inst/cnt_pulse_num[11]} {reflectometer_inst/generator_inst/cnt_pulse_num[12]} {reflectometer_inst/generator_inst/cnt_pulse_num[13]} {reflectometer_inst/generator_inst/cnt_pulse_num[14]} {reflectometer_inst/generator_inst/cnt_pulse_num[15]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2] -set_property port_width 32 [get_debug_ports u_ila_1/probe2] -connect_debug_port u_ila_1/probe2 [get_nets [list {dac_pulse_period[0]} {dac_pulse_period[1]} {dac_pulse_period[2]} {dac_pulse_period[3]} {dac_pulse_period[4]} {dac_pulse_period[5]} {dac_pulse_period[6]} {dac_pulse_period[7]} {dac_pulse_period[8]} {dac_pulse_period[9]} {dac_pulse_period[10]} {dac_pulse_period[11]} {dac_pulse_period[12]} {dac_pulse_period[13]} {dac_pulse_period[14]} {dac_pulse_period[15]} {dac_pulse_period[16]} {dac_pulse_period[17]} {dac_pulse_period[18]} {dac_pulse_period[19]} {dac_pulse_period[20]} {dac_pulse_period[21]} {dac_pulse_period[22]} {dac_pulse_period[23]} {dac_pulse_period[24]} {dac_pulse_period[25]} {dac_pulse_period[26]} {dac_pulse_period[27]} {dac_pulse_period[28]} {dac_pulse_period[29]} {dac_pulse_period[30]} {dac_pulse_period[31]}]] +set_property port_width 14 [get_debug_ports u_ila_1/probe2] +connect_debug_port u_ila_1/probe2 [get_nets [list {reflectometer_inst/dac_pulse_height[0]} {reflectometer_inst/dac_pulse_height[1]} {reflectometer_inst/dac_pulse_height[2]} {reflectometer_inst/dac_pulse_height[3]} {reflectometer_inst/dac_pulse_height[4]} {reflectometer_inst/dac_pulse_height[5]} {reflectometer_inst/dac_pulse_height[6]} {reflectometer_inst/dac_pulse_height[7]} {reflectometer_inst/dac_pulse_height[8]} {reflectometer_inst/dac_pulse_height[9]} {reflectometer_inst/dac_pulse_height[10]} {reflectometer_inst/dac_pulse_height[11]} {reflectometer_inst/dac_pulse_height[12]} {reflectometer_inst/dac_pulse_height[13]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3] set_property port_width 32 [get_debug_ports u_ila_1/probe3] -connect_debug_port u_ila_1/probe3 [get_nets [list {dac_pulse_width[0]} {dac_pulse_width[1]} {dac_pulse_width[2]} {dac_pulse_width[3]} {dac_pulse_width[4]} {dac_pulse_width[5]} {dac_pulse_width[6]} {dac_pulse_width[7]} {dac_pulse_width[8]} {dac_pulse_width[9]} {dac_pulse_width[10]} {dac_pulse_width[11]} {dac_pulse_width[12]} {dac_pulse_width[13]} {dac_pulse_width[14]} {dac_pulse_width[15]} {dac_pulse_width[16]} {dac_pulse_width[17]} {dac_pulse_width[18]} {dac_pulse_width[19]} {dac_pulse_width[20]} {dac_pulse_width[21]} {dac_pulse_width[22]} {dac_pulse_width[23]} {dac_pulse_width[24]} {dac_pulse_width[25]} {dac_pulse_width[26]} {dac_pulse_width[27]} {dac_pulse_width[28]} {dac_pulse_width[29]} {dac_pulse_width[30]} {dac_pulse_width[31]}]] +connect_debug_port u_ila_1/probe3 [get_nets [list {reflectometer_inst/dac_pulse_width[0]} {reflectometer_inst/dac_pulse_width[1]} {reflectometer_inst/dac_pulse_width[2]} {reflectometer_inst/dac_pulse_width[3]} {reflectometer_inst/dac_pulse_width[4]} {reflectometer_inst/dac_pulse_width[5]} {reflectometer_inst/dac_pulse_width[6]} {reflectometer_inst/dac_pulse_width[7]} {reflectometer_inst/dac_pulse_width[8]} {reflectometer_inst/dac_pulse_width[9]} {reflectometer_inst/dac_pulse_width[10]} {reflectometer_inst/dac_pulse_width[11]} {reflectometer_inst/dac_pulse_width[12]} {reflectometer_inst/dac_pulse_width[13]} {reflectometer_inst/dac_pulse_width[14]} {reflectometer_inst/dac_pulse_width[15]} {reflectometer_inst/dac_pulse_width[16]} {reflectometer_inst/dac_pulse_width[17]} {reflectometer_inst/dac_pulse_width[18]} {reflectometer_inst/dac_pulse_width[19]} {reflectometer_inst/dac_pulse_width[20]} {reflectometer_inst/dac_pulse_width[21]} {reflectometer_inst/dac_pulse_width[22]} {reflectometer_inst/dac_pulse_width[23]} {reflectometer_inst/dac_pulse_width[24]} {reflectometer_inst/dac_pulse_width[25]} {reflectometer_inst/dac_pulse_width[26]} {reflectometer_inst/dac_pulse_width[27]} {reflectometer_inst/dac_pulse_width[28]} {reflectometer_inst/dac_pulse_width[29]} {reflectometer_inst/dac_pulse_width[30]} {reflectometer_inst/dac_pulse_width[31]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4] set_property port_width 16 [get_debug_ports u_ila_1/probe4] -connect_debug_port u_ila_1/probe4 [get_nets [list {generator_inst/cnt_pulse_num[0]} {generator_inst/cnt_pulse_num[1]} {generator_inst/cnt_pulse_num[2]} {generator_inst/cnt_pulse_num[3]} {generator_inst/cnt_pulse_num[4]} {generator_inst/cnt_pulse_num[5]} {generator_inst/cnt_pulse_num[6]} {generator_inst/cnt_pulse_num[7]} {generator_inst/cnt_pulse_num[8]} {generator_inst/cnt_pulse_num[9]} {generator_inst/cnt_pulse_num[10]} {generator_inst/cnt_pulse_num[11]} {generator_inst/cnt_pulse_num[12]} {generator_inst/cnt_pulse_num[13]} {generator_inst/cnt_pulse_num[14]} {generator_inst/cnt_pulse_num[15]}]] +connect_debug_port u_ila_1/probe4 [get_nets [list {reflectometer_inst/dac_pulse_num[0]} {reflectometer_inst/dac_pulse_num[1]} {reflectometer_inst/dac_pulse_num[2]} {reflectometer_inst/dac_pulse_num[3]} {reflectometer_inst/dac_pulse_num[4]} {reflectometer_inst/dac_pulse_num[5]} {reflectometer_inst/dac_pulse_num[6]} {reflectometer_inst/dac_pulse_num[7]} {reflectometer_inst/dac_pulse_num[8]} {reflectometer_inst/dac_pulse_num[9]} {reflectometer_inst/dac_pulse_num[10]} {reflectometer_inst/dac_pulse_num[11]} {reflectometer_inst/dac_pulse_num[12]} {reflectometer_inst/dac_pulse_num[13]} {reflectometer_inst/dac_pulse_num[14]} {reflectometer_inst/dac_pulse_num[15]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5] set_property port_width 32 [get_debug_ports u_ila_1/probe5] -connect_debug_port u_ila_1/probe5 [get_nets [list {generator_inst/pulse_width_reg[0]} {generator_inst/pulse_width_reg[1]} {generator_inst/pulse_width_reg[2]} {generator_inst/pulse_width_reg[3]} {generator_inst/pulse_width_reg[4]} {generator_inst/pulse_width_reg[5]} {generator_inst/pulse_width_reg[6]} {generator_inst/pulse_width_reg[7]} {generator_inst/pulse_width_reg[8]} {generator_inst/pulse_width_reg[9]} {generator_inst/pulse_width_reg[10]} {generator_inst/pulse_width_reg[11]} {generator_inst/pulse_width_reg[12]} {generator_inst/pulse_width_reg[13]} {generator_inst/pulse_width_reg[14]} {generator_inst/pulse_width_reg[15]} {generator_inst/pulse_width_reg[16]} {generator_inst/pulse_width_reg[17]} {generator_inst/pulse_width_reg[18]} {generator_inst/pulse_width_reg[19]} {generator_inst/pulse_width_reg[20]} {generator_inst/pulse_width_reg[21]} {generator_inst/pulse_width_reg[22]} {generator_inst/pulse_width_reg[23]} {generator_inst/pulse_width_reg[24]} {generator_inst/pulse_width_reg[25]} {generator_inst/pulse_width_reg[26]} {generator_inst/pulse_width_reg[27]} {generator_inst/pulse_width_reg[28]} {generator_inst/pulse_width_reg[29]} {generator_inst/pulse_width_reg[30]} {generator_inst/pulse_width_reg[31]}]] +connect_debug_port u_ila_1/probe5 [get_nets [list {reflectometer_inst/dac_pulse_period[0]} {reflectometer_inst/dac_pulse_period[1]} {reflectometer_inst/dac_pulse_period[2]} {reflectometer_inst/dac_pulse_period[3]} {reflectometer_inst/dac_pulse_period[4]} {reflectometer_inst/dac_pulse_period[5]} {reflectometer_inst/dac_pulse_period[6]} {reflectometer_inst/dac_pulse_period[7]} {reflectometer_inst/dac_pulse_period[8]} {reflectometer_inst/dac_pulse_period[9]} {reflectometer_inst/dac_pulse_period[10]} {reflectometer_inst/dac_pulse_period[11]} {reflectometer_inst/dac_pulse_period[12]} {reflectometer_inst/dac_pulse_period[13]} {reflectometer_inst/dac_pulse_period[14]} {reflectometer_inst/dac_pulse_period[15]} {reflectometer_inst/dac_pulse_period[16]} {reflectometer_inst/dac_pulse_period[17]} {reflectometer_inst/dac_pulse_period[18]} {reflectometer_inst/dac_pulse_period[19]} {reflectometer_inst/dac_pulse_period[20]} {reflectometer_inst/dac_pulse_period[21]} {reflectometer_inst/dac_pulse_period[22]} {reflectometer_inst/dac_pulse_period[23]} {reflectometer_inst/dac_pulse_period[24]} {reflectometer_inst/dac_pulse_period[25]} {reflectometer_inst/dac_pulse_period[26]} {reflectometer_inst/dac_pulse_period[27]} {reflectometer_inst/dac_pulse_period[28]} {reflectometer_inst/dac_pulse_period[29]} {reflectometer_inst/dac_pulse_period[30]} {reflectometer_inst/dac_pulse_period[31]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6] -set_property port_width 32 [get_debug_ports u_ila_1/probe6] -connect_debug_port u_ila_1/probe6 [get_nets [list {generator_inst/pulse_period_reg[0]} {generator_inst/pulse_period_reg[1]} {generator_inst/pulse_period_reg[2]} {generator_inst/pulse_period_reg[3]} {generator_inst/pulse_period_reg[4]} {generator_inst/pulse_period_reg[5]} {generator_inst/pulse_period_reg[6]} {generator_inst/pulse_period_reg[7]} {generator_inst/pulse_period_reg[8]} {generator_inst/pulse_period_reg[9]} {generator_inst/pulse_period_reg[10]} {generator_inst/pulse_period_reg[11]} {generator_inst/pulse_period_reg[12]} {generator_inst/pulse_period_reg[13]} {generator_inst/pulse_period_reg[14]} {generator_inst/pulse_period_reg[15]} {generator_inst/pulse_period_reg[16]} {generator_inst/pulse_period_reg[17]} {generator_inst/pulse_period_reg[18]} {generator_inst/pulse_period_reg[19]} {generator_inst/pulse_period_reg[20]} {generator_inst/pulse_period_reg[21]} {generator_inst/pulse_period_reg[22]} {generator_inst/pulse_period_reg[23]} {generator_inst/pulse_period_reg[24]} {generator_inst/pulse_period_reg[25]} {generator_inst/pulse_period_reg[26]} {generator_inst/pulse_period_reg[27]} {generator_inst/pulse_period_reg[28]} {generator_inst/pulse_period_reg[29]} {generator_inst/pulse_period_reg[30]} {generator_inst/pulse_period_reg[31]}]] +set_property port_width 14 [get_debug_ports u_ila_1/probe6] +connect_debug_port u_ila_1/probe6 [get_nets [list {reflectometer_inst/p2_data[0]} {reflectometer_inst/p2_data[1]} {reflectometer_inst/p2_data[2]} {reflectometer_inst/p2_data[3]} {reflectometer_inst/p2_data[4]} {reflectometer_inst/p2_data[5]} {reflectometer_inst/p2_data[6]} {reflectometer_inst/p2_data[7]} {reflectometer_inst/p2_data[8]} {reflectometer_inst/p2_data[9]} {reflectometer_inst/p2_data[10]} {reflectometer_inst/p2_data[11]} {reflectometer_inst/p2_data[12]} {reflectometer_inst/p2_data[13]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7] -set_property port_width 32 [get_debug_ports u_ila_1/probe7] -connect_debug_port u_ila_1/probe7 [get_nets [list {generator_inst/cnt_period[0]} {generator_inst/cnt_period[1]} {generator_inst/cnt_period[2]} {generator_inst/cnt_period[3]} {generator_inst/cnt_period[4]} {generator_inst/cnt_period[5]} {generator_inst/cnt_period[6]} {generator_inst/cnt_period[7]} {generator_inst/cnt_period[8]} {generator_inst/cnt_period[9]} {generator_inst/cnt_period[10]} {generator_inst/cnt_period[11]} {generator_inst/cnt_period[12]} {generator_inst/cnt_period[13]} {generator_inst/cnt_period[14]} {generator_inst/cnt_period[15]} {generator_inst/cnt_period[16]} {generator_inst/cnt_period[17]} {generator_inst/cnt_period[18]} {generator_inst/cnt_period[19]} {generator_inst/cnt_period[20]} {generator_inst/cnt_period[21]} {generator_inst/cnt_period[22]} {generator_inst/cnt_period[23]} {generator_inst/cnt_period[24]} {generator_inst/cnt_period[25]} {generator_inst/cnt_period[26]} {generator_inst/cnt_period[27]} {generator_inst/cnt_period[28]} {generator_inst/cnt_period[29]} {generator_inst/cnt_period[30]} {generator_inst/cnt_period[31]}]] +set_property port_width 1 [get_debug_ports u_ila_1/probe7] +connect_debug_port u_ila_1/probe7 [get_nets [list reflectometer_inst/dac_rst]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8] set_property port_width 1 [get_debug_ports u_ila_1/probe8] -connect_debug_port u_ila_1/probe8 [get_nets [list dac_rst]] +connect_debug_port u_ila_1/probe8 [get_nets [list reflectometer_inst/dac_start]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9] set_property port_width 1 [get_debug_ports u_ila_1/probe9] -connect_debug_port u_ila_1/probe9 [get_nets [list dac_start]] +connect_debug_port u_ila_1/probe9 [get_nets [list reflectometer_inst/generator_inst/enable]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10] set_property port_width 1 [get_debug_ports u_ila_1/probe10] -connect_debug_port u_ila_1/probe10 [get_nets [list debug_dac_OBUF]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11] -set_property port_width 1 [get_debug_ports u_ila_1/probe11] -connect_debug_port u_ila_1/probe11 [get_nets [list generator_inst/enable]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12] -set_property port_width 1 [get_debug_ports u_ila_1/probe12] -connect_debug_port u_ila_1/probe12 [get_nets [list sample_done]] +connect_debug_port u_ila_1/probe10 [get_nets [list reflectometer_inst/sample_done]] create_debug_core u_ila_2 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2] -set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_2] -set_property C_ADV_TRIGGER true [get_debug_cores u_ila_2] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2] set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2] -set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_2] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2] set_property C_TRIGIN_EN false [get_debug_cores u_ila_2] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2] set_property port_width 1 [get_debug_ports u_ila_2/clk] -connect_debug_port u_ila_2/clk [get_nets [list rgmii_rxc_IBUF_BUFG]] +connect_debug_port u_ila_2/clk [get_nets [list e_gtxc_OBUF_BUFG]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0] -set_property port_width 3 [get_debug_ports u_ila_2/probe0] -connect_debug_port u_ila_2/probe0 [get_nets [list {accumulator_top_dut/output_async_fifo/rd_state[0]} {accumulator_top_dut/output_async_fifo/rd_state[1]} {accumulator_top_dut/output_async_fifo/rd_state[2]}]] +set_property port_width 8 [get_debug_ports u_ila_2/probe0] +connect_debug_port u_ila_2/probe0 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]] create_debug_port u_ila_2 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1] set_property port_width 8 [get_debug_ports u_ila_2/probe1] connect_debug_port u_ila_2/probe1 [get_nets [list {s_axis_tx_tdata[0]} {s_axis_tx_tdata[1]} {s_axis_tx_tdata[2]} {s_axis_tx_tdata[3]} {s_axis_tx_tdata[4]} {s_axis_tx_tdata[5]} {s_axis_tx_tdata[6]} {s_axis_tx_tdata[7]}]] create_debug_port u_ila_2 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2] -set_property port_width 8 [get_debug_ports u_ila_2/probe2] -connect_debug_port u_ila_2/probe2 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]] +set_property port_width 3 [get_debug_ports u_ila_2/probe2] +connect_debug_port u_ila_2/probe2 [get_nets [list {reflectometer_inst/accumulator_top_dut/output_async_fifo/rd_state[0]} {reflectometer_inst/accumulator_top_dut/output_async_fifo/rd_state[1]} {reflectometer_inst/accumulator_top_dut/output_async_fifo/rd_state[2]}]] create_debug_port u_ila_2 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3] -set_property port_width 1 [get_debug_ports u_ila_2/probe3] -connect_debug_port u_ila_2/probe3 [get_nets [list m_axis_rx_tlast]] +set_property port_width 3 [get_debug_ports u_ila_2/probe3] +connect_debug_port u_ila_2/probe3 [get_nets [list {reflectometer_inst/udp_ctrl_inst/eth_state[0]} {reflectometer_inst/udp_ctrl_inst/eth_state[1]} {reflectometer_inst/udp_ctrl_inst/eth_state[2]}]] create_debug_port u_ila_2 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4] set_property port_width 1 [get_debug_ports u_ila_2/probe4] -connect_debug_port u_ila_2/probe4 [get_nets [list m_axis_rx_tready]] +connect_debug_port u_ila_2/probe4 [get_nets [list reflectometer_inst/udp_ctrl_inst/busy_flag_eth]] create_debug_port u_ila_2 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5] set_property port_width 1 [get_debug_ports u_ila_2/probe5] -connect_debug_port u_ila_2/probe5 [get_nets [list m_axis_rx_tvalid]] +connect_debug_port u_ila_2/probe5 [get_nets [list m_axis_rx_tlast]] create_debug_port u_ila_2 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe6] set_property port_width 1 [get_debug_ports u_ila_2/probe6] -connect_debug_port u_ila_2/probe6 [get_nets [list req_ready]] +connect_debug_port u_ila_2/probe6 [get_nets [list m_axis_rx_tready]] create_debug_port u_ila_2 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe7] set_property port_width 1 [get_debug_ports u_ila_2/probe7] -connect_debug_port u_ila_2/probe7 [get_nets [list s_axis_tx_tlast]] +connect_debug_port u_ila_2/probe7 [get_nets [list m_axis_rx_tvalid]] create_debug_port u_ila_2 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe8] set_property port_width 1 [get_debug_ports u_ila_2/probe8] -connect_debug_port u_ila_2/probe8 [get_nets [list s_axis_tx_tready]] +connect_debug_port u_ila_2/probe8 [get_nets [list req_ready]] create_debug_port u_ila_2 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe9] set_property port_width 1 [get_debug_ports u_ila_2/probe9] -connect_debug_port u_ila_2/probe9 [get_nets [list s_axis_tx_tvalid]] +connect_debug_port u_ila_2/probe9 [get_nets [list s_axis_tx_tlast]] create_debug_port u_ila_2 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe10] set_property port_width 1 [get_debug_ports u_ila_2/probe10] -connect_debug_port u_ila_2/probe10 [get_nets [list send_req]] +connect_debug_port u_ila_2/probe10 [get_nets [list s_axis_tx_tready]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe11] +set_property port_width 1 [get_debug_ports u_ila_2/probe11] +connect_debug_port u_ila_2/probe11 [get_nets [list s_axis_tx_tvalid]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe12] +set_property port_width 1 [get_debug_ports u_ila_2/probe12] +connect_debug_port u_ila_2/probe12 [get_nets [list send_req]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] -connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG] +connect_debug_port dbg_hub/clk [get_nets e_gtxc_OBUF_BUFG] diff --git a/designs/reflectometer_prototype/ip/clk_wiz_ctrl_inst.xci b/designs/reflectometer_prototype/ip/clk_wiz_ctrl_inst.xci new file mode 100644 index 0000000..3b43b73 --- /dev/null +++ b/designs/reflectometer_prototype/ip/clk_wiz_ctrl_inst.xci @@ -0,0 +1,689 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "clk_wiz_ctrl_inst", + "component_reference": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "16", + "gen_directory": "../../../../eth_generator_top.gen/sources_1/ip/clk_wiz_ctrl_inst", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "user", "usage": "all" } ], + "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ], + "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ], + "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ], + "PRIM_IN_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ], + "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ], + "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ], + "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ], + "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ], + "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ], + "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN1_JITTER_PS": [ { "value": "50.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], + "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ], + "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ], + "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], + "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], + "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], + "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], + "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], + "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], + "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], + "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], + "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "16.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.750", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ], + "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ], + "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": 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"value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "ENABLE_CDDC": [ { "value": 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} ], + "C_PRIM_IN_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ], + "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ], + "C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ], + "C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ], + "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ], + "C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_NUM_OUT_CLKS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ], + "C_INCLK_SUM_ROW1": [ { "value": "__primary_________200.000____________0.010", "resolve_type": "generated", "usage": "all" } ], + "C_INCLK_SUM_ROW2": [ { "value": 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"value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", 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"1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "16.875", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_DIVCLK_DIVIDE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.750", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", 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"resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + 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"usage": "all" } ], + "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ], + "C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ], + "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ], + "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ], + "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ], + "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ], + "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ], + "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ], + "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ], + "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ], + "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ], + "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ], + "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ], + "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ], + "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ], + "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ], + "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ], + "C_CLKIN1_JITTER_PS": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ], + "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ], + "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ], + "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ], + "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE2_AUTO": [ { "value": "1.9259259259259258", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE3_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE4_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE5_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE6_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE7_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "125.00000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "64.90385", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_D_MAX": [ { "value": "80.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_VCO_MAX": [ { "value": "1200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "artix7" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7a35t" } ], + "PACKAGE": [ { "value": "fgg484" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "16" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../eth_generator_top.gen/sources_1/ip/clk_wiz_ctrl_inst" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2025.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "reset": [ { "direction": "in", "driver_value": "0" } ], + "clk_in1": [ { "direction": "in" } ], + "clk_out1": [ { "direction": "out" } ], + "clk_out2": [ { "direction": "out" } ], + "locked": [ { "direction": "out" } ] + }, + "interfaces": { + "reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "reset" } ] + } + }, + "clock_CLK_IN1": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], + "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ] + }, + "port_maps": { + "CLK_IN1": [ { "physical_name": "clk_in1" } ] + } + }, + "clock_CLK_OUT1": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "master", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK_OUT1": [ { "physical_name": "clk_out1" } ] + } + }, + "clock_CLK_OUT2": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "master", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK_OUT2": [ { "physical_name": "clk_out2" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/designs/reflectometer_prototype/prototype.sv b/designs/reflectometer_prototype/prototype.sv new file mode 100644 index 0000000..6470abf --- /dev/null +++ b/designs/reflectometer_prototype/prototype.sv @@ -0,0 +1,172 @@ +`timescale 1 ns / 1 ns + +module prototype_top #( + parameter int unsigned DAC_DATA_WIDTH = 14, + parameter int unsigned ADC_DATA_WIDTH = 12, + parameter PACK_FACTOR = 1, + parameter PROCESS_MODE = 0, + parameter ACCUM_WIDTH = 32, + parameter N_MAX = 4096, + parameter WINDOW_SIZE = 65, + parameter PACKET_SIZE = 1024 +)( + input sys_clk_p, // system clock positive + input sys_clk_n, // system clock negative + input rst_n, // reset ,low active + output [3:0] led, // display network rate status + output e_reset, // phy reset + output e_mdc, // phy emdio clock + inout e_mdio, // phy emdio data + input e_rxc, // 125Mhz ethernet gmii rx clock + input e_rxdv, // GMII recieving data valid + input e_rxer, // GMII recieving data error + input [7:0] e_rxd, // GMII recieving data + + input e_txc, // 25Mhz ethernet mii tx clock + output e_gtxc, // 125Mhz ethernet gmii tx clock + output e_txen, // GMII sending data valid + output e_txer, // GMII sending data error + output[7:0] e_txd, // GMII sending data + + // analog + output da2_clk, + output da2_wrt, + output [DAC_DATA_WIDTH-1:0] da2_data, + + output ch2_clk, + input ch2_otr, + input [ADC_DATA_WIDTH-1:0] ch2_data + ); + + wire sys_clk; //single end clock + wire [31:0] pack_total_len ; //package length + wire [1:0] speed ; //net speed select + wire link ; //link status + wire erxdv ; + wire [7:0] erxd ; + wire e_tx_en ; + wire [7:0] etxd ; + wire e_rst_n ; + assign e_gtxc = e_rxc; + assign e_reset = 1'b1; + + // generate single end clock + + IBUFDS sys_clk_ibufgds + ( + .O (sys_clk ), + .I (sys_clk_p ), + .IB (sys_clk_n ) + ); + + + // Different conversion of GMII data according to different network speeds + gmii_arbi arbi_inst + ( + .clk (e_gtxc ), + .rst_n (rst_n ), + .speed (2'b10 ), + .link (1'b1 ), + .pack_total_len (pack_total_len ), + .e_rst_n (e_rst_n ), + .gmii_rx_dv (e_rxdv ), + .gmii_rxd (e_rxd ), + .gmii_tx_en (e_tx_en ), + .gmii_txd (etxd ), + .e_rx_dv (erxdv ), + .e_rxd (erxd ), + .e_tx_en (e_txen ), + .e_txd (e_txd ) + ); + + // ------------------------------------------------------------ + // axis_mac interface + // ------------------------------------------------------------ + wire req_ready; + + wire send_req; + + wire [7:0] s_axis_tx_tdata; + wire s_axis_tx_tvalid; + wire s_axis_tx_tready; + wire s_axis_tx_tlast; + + wire [7:0] m_axis_rx_tdata; + wire m_axis_rx_tvalid; + wire m_axis_rx_tready; + wire m_axis_rx_tlast; + + // ------------------------------------------------------------ + // axis_mac + // ------------------------------------------------------------ + axis_mac axis_mac0 + ( + .gmii_tx_clk (e_gtxc), + .gmii_rx_clk (e_rxc), + .rst_n (e_rst_n), + + .gmii_rx_dv (erxdv), + .gmii_rxd (erxd), + .gmii_tx_en (e_tx_en), + .gmii_txd (etxd), + + .send_req (send_req), + .data_length (PACKET_SIZE), + .req_ready (req_ready), + + .s_axis_tx_tdata (s_axis_tx_tdata), + .s_axis_tx_tvalid (s_axis_tx_tvalid), + .s_axis_tx_tready (s_axis_tx_tready), + .s_axis_tx_tlast (s_axis_tx_tlast), + + .m_axis_rx_tdata (m_axis_rx_tdata), + .m_axis_rx_tvalid (m_axis_rx_tvalid), + .m_axis_rx_tready (m_axis_rx_tready), + .m_axis_rx_tlast (m_axis_rx_tlast) + ); + + // reflectometer base module + reflectometer_top #( + .PROCESS_MODE(PROCESS_MODE), + .PACK_FACTOR(PACK_FACTOR), + .ACCUM_WIDTH(ACCUM_WIDTH), + .N_MAX(N_MAX), + .WINDOW_SIZE(WINDOW_SIZE), + .PACKET_SIZE(PACKET_SIZE), + .ADC_DATA_WIDTH(ADC_DATA_WIDTH), + .DAC_DATA_WIDTH(DAC_DATA_WIDTH) + ) reflectometer_inst ( + .sys_clk (sys_clk), + .rst_n (rst_n), + + .led(led), + + .gmii_tx_clk (e_gtxc), + .gmii_rx_clk (e_rxc), + + .s_axis_tx_tdata (s_axis_tx_tdata), + .s_axis_tx_tvalid (s_axis_tx_tvalid), + .s_axis_tx_tready (s_axis_tx_tready), + .s_axis_tx_tlast (s_axis_tx_tlast), + + .m_axis_rx_tdata (m_axis_rx_tdata), + .m_axis_rx_tvalid (m_axis_rx_tvalid), + .m_axis_rx_tready (m_axis_rx_tready), + .m_axis_rx_tlast (m_axis_rx_tlast), + + // axis_mac + .req_ready(req_ready), + .send_req(send_req), + + // DAC + .p2_clk(da2_clk), + .p2_data(da2_data), + .p2_wrt(da2_wrt), + + // ADC + .ch2_clk(ch2_clk), + .ch2_data(ch2_data), + .ch2_otr(ch2_otr) + ); + +endmodule \ No newline at end of file diff --git a/designs/reflectometer_without_eth/Makefile b/designs/reflectometer_without_eth/Makefile deleted file mode 100644 index e69de29..0000000 diff --git a/designs/reflectometer_without_eth/debug.xdc b/designs/reflectometer_without_eth/debug.xdc deleted file mode 100644 index 8307e09..0000000 --- a/designs/reflectometer_without_eth/debug.xdc +++ /dev/null @@ -1,153 +0,0 @@ -set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst] - - -create_debug_core u_ila_0 ila -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] -set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] -set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] -set_property port_width 1 [get_debug_ports u_ila_0/clk] -connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -set_property port_width 16 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {accumulator_top_dut/accum_main/adder_dut/cnt[0]} {accumulator_top_dut/accum_main/adder_dut/cnt[1]} {accumulator_top_dut/accum_main/adder_dut/cnt[2]} {accumulator_top_dut/accum_main/adder_dut/cnt[3]} {accumulator_top_dut/accum_main/adder_dut/cnt[4]} {accumulator_top_dut/accum_main/adder_dut/cnt[5]} {accumulator_top_dut/accum_main/adder_dut/cnt[6]} {accumulator_top_dut/accum_main/adder_dut/cnt[7]} {accumulator_top_dut/accum_main/adder_dut/cnt[8]} {accumulator_top_dut/accum_main/adder_dut/cnt[9]} {accumulator_top_dut/accum_main/adder_dut/cnt[10]} {accumulator_top_dut/accum_main/adder_dut/cnt[11]} {accumulator_top_dut/accum_main/adder_dut/cnt[12]} {accumulator_top_dut/accum_main/adder_dut/cnt[13]} {accumulator_top_dut/accum_main/adder_dut/cnt[14]} {accumulator_top_dut/accum_main/adder_dut/cnt[15]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -set_property port_width 4 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {accumulator_top_dut/accum_main/wr_state[0]} {accumulator_top_dut/accum_main/wr_state[1]} {accumulator_top_dut/accum_main/wr_state[2]} {accumulator_top_dut/accum_main/wr_state[3]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -set_property port_width 3 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {accumulator_top_dut/output_async_fifo/wr_state[0]} {accumulator_top_dut/output_async_fifo/wr_state[1]} {accumulator_top_dut/output_async_fifo/wr_state[2]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -set_property port_width 32 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {adc_pulse_period[0]} {adc_pulse_period[1]} {adc_pulse_period[2]} {adc_pulse_period[3]} {adc_pulse_period[4]} {adc_pulse_period[5]} {adc_pulse_period[6]} {adc_pulse_period[7]} {adc_pulse_period[8]} {adc_pulse_period[9]} {adc_pulse_period[10]} {adc_pulse_period[11]} {adc_pulse_period[12]} {adc_pulse_period[13]} {adc_pulse_period[14]} {adc_pulse_period[15]} {adc_pulse_period[16]} {adc_pulse_period[17]} {adc_pulse_period[18]} {adc_pulse_period[19]} {adc_pulse_period[20]} {adc_pulse_period[21]} {adc_pulse_period[22]} {adc_pulse_period[23]} {adc_pulse_period[24]} {adc_pulse_period[25]} {adc_pulse_period[26]} {adc_pulse_period[27]} {adc_pulse_period[28]} {adc_pulse_period[29]} {adc_pulse_period[30]} {adc_pulse_period[31]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -set_property port_width 12 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {ch2_data_IBUF[0]} {ch2_data_IBUF[1]} {ch2_data_IBUF[2]} {ch2_data_IBUF[3]} {ch2_data_IBUF[4]} {ch2_data_IBUF[5]} {ch2_data_IBUF[6]} {ch2_data_IBUF[7]} {ch2_data_IBUF[8]} {ch2_data_IBUF[9]} {ch2_data_IBUF[10]} {ch2_data_IBUF[11]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -set_property port_width 16 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {adc_pulse_num[0]} {adc_pulse_num[1]} {adc_pulse_num[2]} {adc_pulse_num[3]} {adc_pulse_num[4]} {adc_pulse_num[5]} {adc_pulse_num[6]} {adc_pulse_num[7]} {adc_pulse_num[8]} {adc_pulse_num[9]} {adc_pulse_num[10]} {adc_pulse_num[11]} {adc_pulse_num[12]} {adc_pulse_num[13]} {adc_pulse_num[14]} {adc_pulse_num[15]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -set_property port_width 12 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {accum_m_axis_tdata[0]} {accum_m_axis_tdata[1]} {accum_m_axis_tdata[2]} {accum_m_axis_tdata[3]} {accum_m_axis_tdata[4]} {accum_m_axis_tdata[5]} {accum_m_axis_tdata[6]} {accum_m_axis_tdata[7]} {accum_m_axis_tdata[8]} {accum_m_axis_tdata[9]} {accum_m_axis_tdata[10]} {accum_m_axis_tdata[11]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] -set_property port_width 1 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list acum_m_axis_tvalid]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] -set_property port_width 1 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list adc_rst]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] -set_property port_width 1 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list adc_start]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] -set_property port_width 1 [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list finish]] -create_debug_core u_ila_1 ila -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1] -set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1] -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1] -set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_1] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1] -set_property port_width 1 [get_debug_ports u_ila_1/clk] -connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0] -set_property port_width 14 [get_debug_ports u_ila_1/probe0] -connect_debug_port u_ila_1/probe0 [get_nets [list {dac_pulse_height[0]} {dac_pulse_height[1]} {dac_pulse_height[2]} {dac_pulse_height[3]} {dac_pulse_height[4]} {dac_pulse_height[5]} {dac_pulse_height[6]} {dac_pulse_height[7]} {dac_pulse_height[8]} {dac_pulse_height[9]} {dac_pulse_height[10]} {dac_pulse_height[11]} {dac_pulse_height[12]} {dac_pulse_height[13]}]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1] -set_property port_width 1 [get_debug_ports u_ila_1/probe1] -connect_debug_port u_ila_1/probe1 [get_nets [list dac_rst]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2] -set_property port_width 1 [get_debug_ports u_ila_1/probe2] -connect_debug_port u_ila_1/probe2 [get_nets [list dac_start]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3] -set_property port_width 1 [get_debug_ports u_ila_1/probe3] -connect_debug_port u_ila_1/probe3 [get_nets [list debug_dac_OBUF]] -create_debug_core u_ila_2 ila -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2] -set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2] -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2] -set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_2] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2] -set_property port_width 1 [get_debug_ports u_ila_2/clk] -connect_debug_port u_ila_2/clk [get_nets [list rgmii_rxc_IBUF_BUFG]] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0] -set_property port_width 3 [get_debug_ports u_ila_2/probe0] -connect_debug_port u_ila_2/probe0 [get_nets [list {accumulator_top_dut/output_async_fifo/rd_state[0]} {accumulator_top_dut/output_async_fifo/rd_state[1]} {accumulator_top_dut/output_async_fifo/rd_state[2]}]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1] -set_property port_width 8 [get_debug_ports u_ila_2/probe1] -connect_debug_port u_ila_2/probe1 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2] -set_property port_width 8 [get_debug_ports u_ila_2/probe2] -connect_debug_port u_ila_2/probe2 [get_nets [list {s_axis_tx_tdata[0]} {s_axis_tx_tdata[1]} {s_axis_tx_tdata[2]} {s_axis_tx_tdata[3]} {s_axis_tx_tdata[4]} {s_axis_tx_tdata[5]} {s_axis_tx_tdata[6]} {s_axis_tx_tdata[7]}]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3] -set_property port_width 3 [get_debug_ports u_ila_2/probe3] -connect_debug_port u_ila_2/probe3 [get_nets [list {udp_ctrl_inst/eth_state[0]} {udp_ctrl_inst/eth_state[1]} {udp_ctrl_inst/eth_state[2]}]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4] -set_property port_width 1 [get_debug_ports u_ila_2/probe4] -connect_debug_port u_ila_2/probe4 [get_nets [list udp_ctrl_inst/axis_hs]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5] -set_property port_width 1 [get_debug_ports u_ila_2/probe5] -connect_debug_port u_ila_2/probe5 [get_nets [list udp_ctrl_inst/busy_flag_eth]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe6] -set_property port_width 1 [get_debug_ports u_ila_2/probe6] -connect_debug_port u_ila_2/probe6 [get_nets [list m_axis_rx_tlast]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe7] -set_property port_width 1 [get_debug_ports u_ila_2/probe7] -connect_debug_port u_ila_2/probe7 [get_nets [list m_axis_rx_tready]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe8] -set_property port_width 1 [get_debug_ports u_ila_2/probe8] -connect_debug_port u_ila_2/probe8 [get_nets [list m_axis_rx_tvalid]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe9] -set_property port_width 1 [get_debug_ports u_ila_2/probe9] -connect_debug_port u_ila_2/probe9 [get_nets [list req_ready]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe10] -set_property port_width 1 [get_debug_ports u_ila_2/probe10] -connect_debug_port u_ila_2/probe10 [get_nets [list s_axis_tx_tlast]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe11] -set_property port_width 1 [get_debug_ports u_ila_2/probe11] -connect_debug_port u_ila_2/probe11 [get_nets [list s_axis_tx_tready]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe12] -set_property port_width 1 [get_debug_ports u_ila_2/probe12] -connect_debug_port u_ila_2/probe12 [get_nets [list s_axis_tx_tvalid]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe13] -set_property port_width 1 [get_debug_ports u_ila_2/probe13] -connect_debug_port u_ila_2/probe13 [get_nets [list send_req]] -set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] -set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] -set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] -connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]