From 5b9469560a82af470643b385db8d1011e4009b0f Mon Sep 17 00:00:00 2001 From: Phil Date: Fri, 15 May 2026 15:08:22 +0300 Subject: [PATCH] infra: update Makefile for synchronizer project --- designs/adc_dac_synchoronizer/Makefile | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/designs/adc_dac_synchoronizer/Makefile b/designs/adc_dac_synchoronizer/Makefile index 4ab32c4..f331cc4 100644 --- a/designs/adc_dac_synchoronizer/Makefile +++ b/designs/adc_dac_synchoronizer/Makefile @@ -7,7 +7,7 @@ # # FPGA settings -FPGA_PART = xc7a35tfgg484-1 +FPGA_PART = xc7a100tfgg484-2 FPGA_TOP = sync_top FPGA_ARCH = artix7 @@ -16,13 +16,19 @@ RTL_DIR = ../../rtl include ../../scripts/vivado.mk + +SYN_FILES += $(sort $(shell find ../../rtl/sampler/src -type f -name '*.sv')) +SYN_FILES += $(sort $(shell find ../../rtl/generator/src -type f -name '*.sv')) SYN_FILES += sync_top.sv -SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \))) +XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci')) -XDC_FILES += ../../constraints/ax7a035b.xdc +XDC_FILES += ../../constraints/ax7102.xdc XDC_FILES += debug.xdc +SYN_FILES += tb_sync_top.sv +SIM_TOP = tb_top + program: $(PROJECT).bit